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Over-ride build_graph in row/col caps to remove incorrect graph error.

This commit is contained in:
mrg 2023-03-01 09:25:56 -08:00
parent 63ba8647fb
commit 58f1b55e08
4 changed files with 28 additions and 0 deletions
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7
compiler/modules/col_cap_bitcell_1port.py
View File

@ -20,3 +20,10 @@ class col_cap_bitcell_1port(bitcell_base):
debug.info(2, "Create col_cap bitcell 1 port object") debug.info(2, "Create col_cap bitcell 1 port object")
self.no_instances = True self.no_instances = True
def build_graph(self, graph, inst_name, port_nets):
"""
Adds edges based on inputs/outputs.
Overrides base class function.
"""
pass

7
compiler/modules/col_cap_bitcell_2port.py
View File

@ -20,3 +20,10 @@ class col_cap_bitcell_2port(bitcell_base):
debug.info(2, "Create col_cap bitcell 2 port object") debug.info(2, "Create col_cap bitcell 2 port object")
self.no_instances = True self.no_instances = True
def build_graph(self, graph, inst_name, port_nets):
"""
Adds edges based on inputs/outputs.
Overrides base class function.
"""
pass

7
compiler/modules/row_cap_bitcell_1port.py
View File

@ -20,3 +20,10 @@ class row_cap_bitcell_1port(bitcell_base):
debug.info(2, "Create row_cap bitcell 1 port object") debug.info(2, "Create row_cap bitcell 1 port object")
self.no_instances = True self.no_instances = True
def build_graph(self, graph, inst_name, port_nets):
"""
Adds edges based on inputs/outputs.
Overrides base class function.
"""
pass

7
compiler/modules/row_cap_bitcell_2port.py
View File

@ -20,3 +20,10 @@ class row_cap_bitcell_2port(bitcell_base):
debug.info(2, "Create row_cap bitcell 2 port object") debug.info(2, "Create row_cap bitcell 2 port object")
self.no_instances = True self.no_instances = True
def build_graph(self, graph, inst_name, port_nets):
"""
Adds edges based on inputs/outputs.
Overrides base class function.
"""
pass