Limit wordline driver size. Place row addr dff near predecoders.

compiler/modules/bank.py

@@ -211,10 +211,11 @@ class bank(design.design):
         self.port_data_offsets[port] = vector(self.main_bitcell_array_left - self.bitcell_array.cell.width, 0)
 
         # UPPER LEFT QUADRANT
-        # To the left of the bitcell array
+        # To the left of the bitcell array above the predecoders and control logic
         x_offset = self.m2_gap + self.port_address.width
         self.port_address_offsets[port] = vector(-x_offset,
                                                  self.main_bitcell_array_bottom)
+        self.predecoder_height = self.port_address.predecoder_height + self.port_address_offsets[port].y
 
         # LOWER LEFT QUADRANT
         # Place the col decoder left aligned with wordline driver

compiler/modules/hierarchical_decoder.py

@@ -314,24 +314,23 @@ class hierarchical_decoder(design.design):
         for i in range(self.no_of_pre3x8):
             self.place_pre3x8(i)
 
+        self.predecode_height = 0
+        if self.no_of_pre2x4 > 0:
+            self.predecode_height = self.pre2x4_inst[-1].uy()
+        if self.no_of_pre3x8 > 0:
+            self.predecode_height = self.pre3x8_inst[-1].uy()
+
     def place_pre2x4(self, num):
         """ Place 2x4 predecoder to the left of the origin """
         
-        if (self.num_inputs == 2):
+        base= vector(-self.pre2_4.width, num * (self.pre2_4.height + self.predecoder_spacing))
-            base = vector(-self.pre2_4.width, 0)
-        else:
-            base= vector(-self.pre2_4.width, num * (self.pre2_4.height + self.predecoder_spacing))
-
         self.pre2x4_inst[num].place(base)
         
     def place_pre3x8(self, num):
         """ Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """
-        if (self.num_inputs == 3):
+        height = self.no_of_pre2x4 * (self.pre2_4.height + self.predecoder_spacing) \
-            offset = vector(-self.pre_3_8.width, 0)
+                 + num * (self.pre3_8.height + self.predecoder_spacing)
-        else:
+        offset = vector(-self.pre3_8.width, height)
-            height = self.no_of_pre2x4 * (self.pre2_4.height + self.predecoder_spacing) + num * (self.pre3_8.height + self.predecoder_spacing)
-            offset = vector(-self.pre3_8.width, height)
-
         self.pre3x8_inst[num].place(offset)
 
     def create_row_decoder(self):

compiler/modules/port_address.py

@@ -153,6 +153,8 @@ class port_address(design.design):
         wordline_driver_offset = vector(self.row_decoder.width, 0)
         self.wordline_driver_inst.place(wordline_driver_offset)
         self.row_decoder_inst.place(row_decoder_offset)
+        # Pass this up
+        self.predecoder_height = self.row_decoder.predecoder_height
 
         self.height = self.row_decoder.height
         self.width = self.wordline_driver_inst.rx()

compiler/sram/sram_1bank.py

@@ -117,7 +117,7 @@ class sram_1bank(sram_base):
         # The row address bits are placed above the control logic aligned on the right.
         x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width
         # It is above the control logic but below the top of the bitcell array
-        y_offset = max(self.control_logic_insts[port].uy(), self.bank_inst.uy() - self.row_addr_dff_insts[port].height)
+        y_offset = max(self.control_logic_insts[port].uy(), self.bank.predecoder_height)
         self.row_addr_pos[port] = vector(x_offset, y_offset)
         self.row_addr_dff_insts[port].place(self.row_addr_pos[port])
 
@@ -125,8 +125,8 @@ class sram_1bank(sram_base):
             port = 1
             # The row address bits are placed above the control logic aligned on the left.
             x_offset = self.control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width
-            # It is below the control logic but below the bottom of the bitcell array
+            # If it can be placed above the predecoder and below the control logic, do it
-            y_offset = min(self.control_logic_insts[port].by(), self.bank_inst.by() + self.row_addr_dff_insts[port].height)
+            y_offset = self.bank.bank_array_ll.y
             self.row_addr_pos[port] = vector(x_offset, y_offset)
             self.row_addr_dff_insts[port].place(self.row_addr_pos[port], mirror="XY")