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Removing unused tech parms. Simplifying redundant parms.

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Matt Guthaus
2019-09-04 16:08:18 -07:00
parent 8c601ce939
commit 585ce63dff
17 changed files with 54 additions and 126 deletions
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compiler/tests/21_hspice_delay_test.py
+1 -1
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@@ -54,7 +54,7 @@ class timing_sram_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"]*4]
loads = [tech.spice["dff_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
compiler/tests/21_model_delay_test.py
+1 -1
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@@ -49,7 +49,7 @@ class model_delay_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"]*4]
loads = [tech.spice["dff_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
# Run a spice characterization
compiler/tests/21_ngspice_delay_test.py
+1 -1
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@@ -47,7 +47,7 @@ class timing_sram_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"]*4]
loads = [tech.spice["dff_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data