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Removing unused tech parms. Simplifying redundant parms.

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Matt Guthaus
2019-09-04 16:08:18 -07:00
parent 8c601ce939
commit 585ce63dff
17 changed files with 54 additions and 126 deletions
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compiler/modules/bitcell_array.py
+1 -1
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@@ -157,7 +157,7 @@ class bitcell_array(design.design):
bl_wire = self.gen_bl_wire()
cell_load = 2 * bl_wire.return_input_cap()
bl_swing = OPTS.rbl_delay_percentage
freq = spice["default_event_rate"]
freq = spice["default_event_frequency"]
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
#Calculate the bitcell power which currently only includes leakage