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Removing unused tech parms. Simplifying redundant parms.

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This commit is contained in:
Matt Guthaus
2019-09-04 16:08:18 -07:00
parent 8c601ce939
commit 585ce63dff
17 changed files with 54 additions and 126 deletions
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compiler/modules/bitcell_array.py
+1 -1
View File
@@ -157,7 +157,7 @@ class bitcell_array(design.design):
bl_wire = self.gen_bl_wire()
cell_load = 2 * bl_wire.return_input_cap()
bl_swing = OPTS.rbl_delay_percentage
freq = spice["default_event_rate"]
freq = spice["default_event_frequency"]
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
#Calculate the bitcell power which currently only includes leakage
compiler/modules/dff.py
+5 -5
View File
@@ -33,9 +33,9 @@ class dff(design.design):
def analytical_power(self, corner, load):
"""Returns dynamic and leakage power. Results in nW"""
c_eff = self.calculate_effective_capacitance(load)
freq = spice["default_event_rate"]
freq = spice["default_event_frequency"]
power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
power_leak = spice["msflop_leakage"]
power_leak = spice["dff_leakage"]
total_power = self.return_power(power_dyn, power_leak)
return total_power
@@ -44,8 +44,8 @@ class dff(design.design):
"""Computes effective capacitance. Results in fF"""
from tech import parameter
c_load = load
c_para = spice["flop_para_cap"]#ff
transition_prob = spice["flop_transition_prob"]
c_para = spice["dff_out_cap"]#ff
transition_prob = 0.5
return transition_prob*(c_load + c_para)
def get_clk_cin(self):
@@ -57,4 +57,4 @@ class dff(design.design):
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/modules/replica_bitcell_array.py
+1 -1
View File
@@ -382,7 +382,7 @@ class replica_bitcell_array(design.design):
bl_wire = self.gen_bl_wire()
cell_load = 2 * bl_wire.return_input_cap()
bl_swing = OPTS.rbl_delay_percentage
freq = spice["default_event_rate"]
freq = spice["default_event_frequency"]
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
#Calculate the bitcell power which currently only includes leakage