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Removing unused tech parms. Simplifying redundant parms.
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@@ -46,7 +46,7 @@ class simulation():
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""" sets feasible timing parameters """
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self.period = tech.spice["feasible_period"]
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self.slew = tech.spice["rise_time"]*2
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self.load = tech.spice["msflop_in_cap"]*4
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self.load = tech.spice["dff_in_cap"]*4
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self.v_high = self.vdd_voltage - tech.spice["v_threshold_typical"]
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self.v_low = tech.spice["v_threshold_typical"]
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@@ -301,7 +301,7 @@ class simulation():
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pin_names.append("WEB{0}".format(port))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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pin_names.append("{0}{1}".format("clk", port))
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if self.write_size:
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for port in write_index:
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@@ -312,7 +312,7 @@ class simulation():
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(dout_name,read_output, i))
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pin_names.append("{0}".format(tech.spice["vdd_name"]))
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pin_names.append("{0}".format(tech.spice["gnd_name"]))
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pin_names.append("{0}".format("vdd"))
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pin_names.append("{0}".format("gnd"))
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return pin_names
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