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fix pinv size bining

This commit is contained in:
jcirimel 2020-06-25 06:32:07 -07:00
parent 8166adc512
commit 57b6d49edb
2 changed files with 17 additions and 7 deletions
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2
compiler/pgates/pgate.py
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@ -379,4 +379,4 @@ class pgate(design.design):
return(scaled_bins) return(scaled_bins)
def bin_accuracy(self, ideal_width, width): def bin_accuracy(self, ideal_width, width):
return abs(1-(ideal_width - width)/ideal_width) return 1-abs((ideal_width - width)/ideal_width)

18
compiler/pgates/pinv.py
View File

@ -31,6 +31,9 @@ class pinv(pgate.pgate):
height is usually the same as the 6t library cell and is measured height is usually the same as the 6t library cell and is measured
from center of rail to rail. from center of rail to rail.
""" """
# binning %error tracker
bin_count = 0
bin_error = 0
def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True): def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True):
@ -166,29 +169,36 @@ class pinv(pgate.pgate):
valid_pmos = [] valid_pmos = []
for bin in pmos_bins: for bin in pmos_bins:
if self.bin_accuracy(self.pmos_width, bin[0]) > accuracy_requirement: if abs(self.bin_accuracy(self.pmos_width, bin[0])) > accuracy_requirement and abs(self.bin_accuracy(self.pmos_width, bin[0])) <= 1:
valid_pmos.append(bin) valid_pmos.append(bin)
valid_pmos.sort(key = operator.itemgetter(1)) valid_pmos.sort(key = operator.itemgetter(1))
valid_nmos = [] valid_nmos = []
for bin in nmos_bins: for bin in nmos_bins:
if self.bin_accuracy(self.nmos_width, bin[0]) > accuracy_requirement: if abs(self.bin_accuracy(self.nmos_width, bin[0])) > accuracy_requirement and abs(self.bin_accuracy(self.nmos_width, bin[0])) <= 1:
valid_nmos.append(bin) valid_nmos.append(bin)
valid_nmos.sort(key = operator.itemgetter(1)) valid_nmos.sort(key = operator.itemgetter(1))
for bin in valid_pmos: for bin in valid_pmos:
if bin[0]/bin[1] < pmos_height_available: if bin[0]/bin[1] < pmos_height_available:
self.pmos_width = bin[0]/bin[1] self.pmos_width = bin[0]/bin[1]
pmos_mults = valid_pmos[0][1] pmos_mults = bin[1]
break break
for bin in valid_nmos: for bin in valid_nmos:
if bin[0]/bin[1] < nmos_height_available: if bin[0]/bin[1] < nmos_height_available:
self.nmos_width = bin[0]/bin[1] self.nmos_width = bin[0]/bin[1]
nmos_mults = valid_pmos[0][1] nmos_mults = bin[1]
break break
self.tx_mults = max(pmos_mults, nmos_mults) self.tx_mults = max(pmos_mults, nmos_mults)
debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("pmos", self.pmos_width, pmos_mults, self.pmos_width * pmos_mults, self.pmos_size * drc("minwidth_tx")))
debug.info(2, "prebinning {0} tx, target: {4}, found {1} x {2} = {3}".format("nmos", self.nmos_width, nmos_mults, self.nmos_width * nmos_mults, self.nmos_size * drc("minwidth_tx")))
pinv.bin_count += 1
pinv.bin_error += abs((self.pmos_width * pmos_mults) - (self.pmos_size * drc("minwidth_tx"))/(self.pmos_size * drc("minwidth_tx")))
pinv.bin_count += 1
pinv.bin_error += abs((self.nmos_width * nmos_mults) - (self.nmos_size * drc("minwidth_tx"))/(self.nmos_size * drc("minwidth_tx")))
debug.info(2, "pinv bin count: {0} pinv bin error: {1} percent error {2}".format(pinv.bin_count, pinv.bin_error, pinv.bin_error/pinv.bin_count))
def add_ptx(self): def add_ptx(self):
""" Create the PMOS and NMOS transistors. """ """ Create the PMOS and NMOS transistors. """