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Order of wordlines and bitlines in bank

This commit is contained in:
mrg 2020-08-18 16:30:38 -07:00
parent 224e359208
commit 5776788574
1 changed files with 14 additions and 6 deletions
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16
compiler/modules/bank.py
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@ -394,11 +394,13 @@ class bank(design.design):
""" Creating Bitcell Array """ """ Creating Bitcell Array """
self.bitcell_array_inst=self.add_inst(name="replica_bitcell_array", self.bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
mod=self.bitcell_array) mod=self.bitcell_array)
# Arrays are always:
# word lines (bottom to top)
# bit lines (left to right)
# vdd
# gnd
temp = [] temp = []
rbl_names = self.bitcell_array.get_rbl_bitline_names()
temp.extend(rbl_names)
bitline_names = self.bitcell_array.get_bitline_names()
temp.extend(bitline_names)
# Replace RBL wordline with wl_en# # Replace RBL wordline with wl_en#
wordline_names = self.bitcell_array.get_wordline_names() wordline_names = self.bitcell_array.get_wordline_names()
@ -414,6 +416,12 @@ class bank(design.design):
# Connect the dummy WL to gnd # Connect the dummy WL to gnd
wordline_names = ["gnd" if x.startswith("dummy") else x for x in wordline_names] wordline_names = ["gnd" if x.startswith("dummy") else x for x in wordline_names]
temp.extend(wordline_names) temp.extend(wordline_names)
rbl_names = self.bitcell_array.get_rbl_bitline_names()
temp.extend(rbl_names)
bitline_names = self.bitcell_array.get_bitline_names()
temp.extend(bitline_names)
temp.append("vdd") temp.append("vdd")
temp.append("gnd") temp.append("gnd")
self.connect_inst(temp) self.connect_inst(temp)