Changed test values to fix tests.

2026-09-07 11:21:14 +02:00 · 2019-02-06 15:27:29 -08:00
parent 01c8405d12
commit 56e79c050b
2 changed files with 19 additions and 14 deletions
@@ -182,7 +182,12 @@ class control_logic(design.design):
            delay_stages = 8
        else:
            delay_stages = 2
-            
+        
+        #Read ports have a shorter s_en delay. The model is not accurate enough to catch this difference
+        #on certain sram configs.
+        if self.port_type == "r":
+            delay_stages+=2
+        
        return (delay_stages, delay_fanout)
        
    def set_sen_wl_delays(self):