luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix typo

This commit is contained in:
Jesse Cirimelli-Low 2021-06-18 18:10:12 -07:00
parent 2dbe928c09
commit 56dc83de47
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/sram/sram_config.py
View File

@ -98,9 +98,9 @@ class sram_config:
+ " Col addr size: {}".format(self.col_addr_size) + " Col addr size: {}".format(self.col_addr_size)
+ " Bank addr size: {}".format(self.bank_addr_size)) + " Bank addr size: {}".format(self.bank_addr_size))
num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_w_ports num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
print(num_ports) print(num_ports)
if num_ports != 1: if num_ports == 1:
if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0): if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0):
debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1) debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1)