mirror of https://github.com/VLSIDA/OpenRAM.git
Extra track in data bus. Remove old code.
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mrg
parent
eb11ac22f3
commit
5626fd182e
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@ -73,10 +73,11 @@ class sram_1bank(sram_base):
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self.data_bus_gap = self.m4_nonpref_pitch * 2
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self.data_bus_gap = self.m4_nonpref_pitch * 2
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# Spare wen are on a separate layer so not included
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# Spare wen are on a separate layer so not included
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self.data_bus_size = [None] * len(self.all_ports)
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# Start with 1 track minimum
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self.data_bus_size = [1] * len(self.all_ports)
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for port in self.all_ports:
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for port in self.all_ports:
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# All ports need the col addr flops
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# All ports need the col addr flops
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self.data_bus_size[port] = self.col_addr_size
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self.data_bus_size[port] += self.col_addr_size
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# Write ports need the data input flops and write mask flops
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# Write ports need the data input flops and write mask flops
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if port in self.write_ports:
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if port in self.write_ports:
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self.data_bus_size[port] += self.num_wmasks + self.word_size
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self.data_bus_size[port] += self.num_wmasks + self.word_size
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@ -324,16 +325,6 @@ class sram_1bank(sram_base):
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self.route_row_addr_dff()
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self.route_row_addr_dff()
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# if self.col_addr_dff:
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# self.route_col_addr_dff()
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# self.route_data_dff()
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# if self.write_size:
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# self.route_wmask_dff()
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# if self.num_spare_cols:
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# self.route_spare_wen_dff()
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for port in self.all_ports:
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for port in self.all_ports:
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self.route_dff(port)
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self.route_dff(port)
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@ -488,137 +479,6 @@ class sram_1bank(sram_base):
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offset=mid_pos)
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offset=mid_pos)
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self.add_path(bank_pin.layer, [mid_pos, bank_pos])
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self.add_path(bank_pin.layer, [mid_pos, bank_pos])
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def route_col_addr_dff(self):
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""" Connect the output of the col flops to the bank pins """
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for port in self.all_ports:
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if port % 2:
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offset = self.col_addr_dff_insts[port].ll() - vector(0, self.col_addr_bus_size)
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else:
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offset = self.col_addr_dff_insts[port].ul() + vector(0, self.col_addr_bus_gap)
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bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)]
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col_addr_bus_offsets = self.create_horizontal_bus(layer="m1",
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offset=offset,
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names=bus_names,
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length=self.col_addr_dff_insts[port].width)
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dff_names = ["dout_{}".format(x) for x in range(self.col_addr_size)]
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data_dff_map = zip(dff_names, bus_names)
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self.connect_horizontal_bus(data_dff_map,
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self.col_addr_dff_insts[port],
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col_addr_bus_offsets)
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bank_names = ["addr{0}_{1}".format(port, x) for x in range(self.col_addr_size)]
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data_bank_map = zip(bank_names, bus_names)
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self.connect_horizontal_bus(data_bank_map,
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self.bank_inst,
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col_addr_bus_offsets)
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def route_data_dff(self):
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""" Connect the output of the data flops to the write driver """
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# This is where the channel will start (y-dimension at least)
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for port in self.write_ports:
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if port % 2:
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offset = self.data_dff_insts[port].ll() - vector(0, self.data_bus_size[port])
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else:
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offset = self.data_dff_insts[port].ul() + vector(0, self.data_bus_gap)
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dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)]
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dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names]
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if self.write_size or self.num_spare_cols:
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for x in dff_names:
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pin = self.data_dff_insts[port].get_pin(x)
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pin_offset = pin.center()
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self.add_via_center(layers=self.m1_stack,
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offset=pin_offset,
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directions=("V", "V"))
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self.add_via_stack_center(from_layer="m2",
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to_layer="m4",
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offset=pin_offset)
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bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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if self.write_size or self.num_spare_cols:
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for x in bank_names:
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pin = self.bank_inst.get_pin(x)
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if port % 2:
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pin_offset = pin.uc()
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else:
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pin_offset = pin.bc()
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer="m4",
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offset=pin_offset)
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route_map = list(zip(bank_pins, dff_pins))
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if self.write_size or self.num_spare_cols:
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layer_stack = self.m3_stack
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else:
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layer_stack = self.m1_stack
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self.create_horizontal_channel_route(netlist=route_map,
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offset=offset,
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layer_stack=layer_stack)
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def route_wmask_dff(self):
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""" Connect the output of the wmask flops to the write mask AND array """
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# This is where the channel will start (y-dimension at least)
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for port in self.write_ports:
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if port % 2:
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offset = self.wmask_dff_insts[port].ll() - vector(0, self.wmask_bus_size)
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else:
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offset = self.wmask_dff_insts[port].ul() + vector(0, self.wmask_bus_gap)
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dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)]
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dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names]
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for x in dff_names:
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offset_pin = self.wmask_dff_insts[port].get_pin(x).center()
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self.add_via_center(layers=self.m1_stack,
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offset=offset_pin,
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directions=("V", "V"))
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bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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for x in bank_names:
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offset_pin = self.bank_inst.get_pin(x).center()
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self.add_via_center(layers=self.m1_stack,
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offset=offset_pin)
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route_map = list(zip(bank_pins, dff_pins))
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self.create_horizontal_channel_route(netlist=route_map,
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offset=offset,
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layer_stack=self.m1_stack)
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def route_spare_wen_dff(self):
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""" Connect the output of the spare write enable flops to the spare write drivers """
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# This is where the channel will start (y-dimension at least)
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for port in self.write_ports:
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if port % 2:
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# for port 0
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offset = self.spare_wen_dff_insts[port].ll() - vector(0, self.spare_wen_bus_size)
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else:
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offset = self.spare_wen_dff_insts[port].ul() + vector(0, self.spare_wen_bus_gap)
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dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)]
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dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names]
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for x in dff_names:
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offset_pin = self.spare_wen_dff_insts[port].get_pin(x).center()
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self.add_via_center(layers=self.m1_stack,
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offset=offset_pin,
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directions=("V", "V"))
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bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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for x in bank_names:
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offset_pin = self.bank_inst.get_pin(x).center()
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self.add_via_center(layers=self.m1_stack,
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offset=offset_pin)
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route_map = list(zip(bank_pins, dff_pins))
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self.create_horizontal_channel_route(netlist=route_map,
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offset=offset,
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layer_stack=self.m1_stack)
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def add_lvs_correspondence_points(self):
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def add_lvs_correspondence_points(self):
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"""
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"""
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This adds some points for easier debugging if LVS goes wrong.
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This adds some points for easier debugging if LVS goes wrong.
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