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copy supply pins to top level in replica array, now passing tests

This commit is contained in:
samuelkcrow 2022-10-19 17:13:54 -07:00
parent f9419e8ff7
commit 55d89fbae8
1 changed files with 10 additions and 2 deletions
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10
compiler/modules/replica_bitcell_array.py
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@ -217,7 +217,7 @@ class replica_bitcell_array(bitcell_base_array):
else: else:
self.replica_col_insts.append(None) self.replica_col_insts.append(None)
# Dummy rows under the bitcell array (connected with with the replica cell wl) # Dummy rows above/below the bitcell array (connected with the replica cell wl)
self.dummy_row_replica_insts = [] self.dummy_row_replica_insts = []
# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
for port in self.all_ports: for port in self.all_ports:
@ -250,6 +250,8 @@ class replica_bitcell_array(bitcell_base_array):
self.add_layout_pins() self.add_layout_pins()
self.route_supplies()
lower_left = self.find_lowest_coords() lower_left = self.find_lowest_coords()
upper_right = self.find_highest_coords() upper_right = self.find_highest_coords()
self.width = upper_right.x - lower_left.x self.width = upper_right.x - lower_left.x
@ -370,6 +372,12 @@ class replica_bitcell_array(bitcell_base_array):
width=pin.width(), width=pin.width(),
height=self.height) height=self.height)
def route_supplies(self):
for inst in self.insts:
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
def analytical_power(self, corner, load): def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW.""" """Power of Bitcell array and bitline in nW."""
# Dynamic Power from Bitline # Dynamic Power from Bitline