mirror of https://github.com/VLSIDA/OpenRAM.git
Fix syntax errors in pgates for super edits
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parent
30976df48f
commit
55814a8f74
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@ -26,7 +26,7 @@ class pgate(design.design):
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def __init__(self, name, height=None, add_wells=True):
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""" Creates a generic cell """
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super().__init__(, name)
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super().__init__(name)
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if height:
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self.height = height
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@ -23,7 +23,7 @@ class precharge(design.design):
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def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"):
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debug.info(2, "creating precharge cell {0}".format(name))
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super().__init__(, name)
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super().__init__(name)
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self.bitcell = factory.create(module_type="bitcell")
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self.beta = parameter["beta"]
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@ -75,7 +75,7 @@ class ptx(design.design):
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# replace periods with underscore for newer spice compatibility
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name = name.replace('.', '_')
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debug.info(3, "creating ptx {0}".format(name))
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super().__init__(, name)
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super().__init__(name)
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self.tx_type = tx_type
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self.mults = mults
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@ -22,7 +22,7 @@ class pwrite_driver(design.design):
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def __init__(self, name, size=0):
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debug.error("pwrite_driver not implemented yet.", -1)
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debug.info(1, "creating pwrite_driver {}".format(name))
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super().__init__(, name)
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super().__init__(name)
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self.size = size
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self.beta = parameter["beta"]
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self.pmos_width = self.beta*self.size*parameter["min_tx_size"]
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@ -21,7 +21,7 @@ class wordline_driver(design.design):
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def __init__(self, name, size=1, height=None):
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debug.info(1, "Creating wordline_driver {}".format(name))
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self.add_comment("size: {}".format(size))
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super().__init__(, name)
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super().__init__(name)
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if height is None:
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b = factory.create(module_type="bitcell")
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