Auto-generate port dependent cell names.

compiler/globals.py

@@ -214,25 +214,18 @@ def setup_bitcell():
             if OPTS.num_r_ports > 0:
                 ports += "{}r".format(OPTS.num_r_ports)
 
-            OPTS.bitcell = "bitcell_"+ports
+            if ports != "":
-            OPTS.replica_bitcell = "replica_bitcell_"+ports
+                OPTS.bitcell_suffix = "_" + ports
-            OPTS.dummy_bitcell = "dummy_bitcell_"+ports
+            OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
-    else:
-        OPTS.replica_bitcell = "replica_" + OPTS.bitcell
-        OPTS.replica_bitcell = "dummy_" + OPTS.bitcell
                 
     # See if bitcell exists
     try:
         __import__(OPTS.bitcell)
-        __import__(OPTS.replica_bitcell)
-        __import__(OPTS.dummy_bitcell)
     except ImportError:
         # Use the pbitcell if we couldn't find a custom bitcell
         # or its custom replica  bitcell
         # Use the pbitcell (and give a warning if not in unit test mode)
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell = "replica_pbitcell"
-        OPTS.replica_bitcell = "dummy_pbitcell"
         if not OPTS.is_unit_test:
             debug.warning("Using the parameterized bitcell which may have suboptimal density.")
     debug.info(1, "Using bitcell: {}".format(OPTS.bitcell))

compiler/modules/col_cap_array.py

@@ -8,6 +8,7 @@ from sram_factory import factory
 from globals import OPTS
 from tech import cell_properties
 
+
 class col_cap_array(bitcell_base_array):
     """
     Generate a dummy row/column for the replica array.
@@ -35,8 +36,7 @@ class col_cap_array(bitcell_base_array):
 
     def add_modules(self):
         """ Add the modules used in this design """
-        # self.dummy_cell = factory.create(module_type="col_cap_bitcell_1rw_1r") # TODO: make module_type generic
+        self.dummy_cell = factory.create(module_type="col_cap_{}".format(OPTS.bitcell))
-        self.dummy_cell = factory.create(module_type="col_cap_bitcell")
         self.add_mod(self.dummy_cell)
 
         self.cell = factory.create(module_type="bitcell")

compiler/modules/dummy_array.py

@@ -38,20 +38,19 @@ class dummy_array(bitcell_base_array):
 
     def add_modules(self):
         """ Add the modules used in this design """
-        self.dummy_cell = factory.create(module_type="dummy_bitcell")
+        self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
         self.add_mod(self.dummy_cell)
 
         self.cell = factory.create(module_type="bitcell")
         
-        
     def create_instances(self):
         """ Create the module instances used in this design """
         self.cell_inst = {}
         for col in range(self.column_size):
             for row in range(self.row_size):
                 name = "bit_r{0}_c{1}".format(row, col)
-                self.cell_inst[row,col]=self.add_inst(name=name,
+                self.cell_inst[row, col]=self.add_inst(name=name,
-                                                      mod=self.dummy_cell)
+                                                       mod=self.dummy_cell)
                 self.connect_inst(self.get_bitcell_pins(col, row))
 
     def input_load(self):
@@ -60,7 +59,7 @@ class dummy_array(bitcell_base_array):
 
     def get_wordline_cin(self):
         """Get the relative input capacitance from the wordline connections in all the bitcell"""
-        #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
+        # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
         bitcell_wl_cin = self.cell.get_wl_cin()
         total_cin = bitcell_wl_cin * self.column_size
         return total_cin

compiler/modules/replica_column.py

@@ -5,12 +5,12 @@
 #
 import debug
 import design
-from tech import drc, cell_properties
+from tech import cell_properties
-import contact
 from sram_factory import factory
 from vector import vector
 from globals import OPTS
 
+
 class replica_column(design.design):
     """
     Generate a replica bitline column for the replica array.
@@ -29,11 +29,12 @@ class replica_column(design.design):
         self.right_rbl = right_rbl
         self.replica_bit = replica_bit
         # left, right, regular rows plus top/bottom dummy cells
-        self.total_size = self.left_rbl+rows+self.right_rbl+2
+        self.total_size = self.left_rbl + rows + self.right_rbl + 2
         self.column_offset = column_offset
 
-        debug.check(replica_bit!=0 and replica_bit!=rows,"Replica bit cannot be the dummy row.")
+        debug.check(replica_bit != 0 and replica_bit != rows,
-        debug.check(replica_bit<=left_rbl or replica_bit>=self.total_size-right_rbl-1,
+                    "Replica bit cannot be the dummy row.")
+        debug.check(replica_bit <= left_rbl or replica_bit >= self.total_size - right_rbl - 1,
                     "Replica bit cannot be in the regular array.")
 
         self.create_netlist()
@@ -46,7 +47,7 @@ class replica_column(design.design):
         self.create_instances()
 
     def create_layout(self):
-        self.height = self.total_size*self.cell.height
+        self.height = self.total_size * self.cell.height
         self.width = self.cell.width
 
         self.place_instances()
@@ -58,25 +59,25 @@ class replica_column(design.design):
 
         for bl_name in self.cell.get_all_bitline_names():
             # In the replica column, these are only outputs!
-            self.add_pin("{0}_{1}".format(bl_name,0), "OUTPUT")
+            self.add_pin("{0}_{1}".format(bl_name, 0), "OUTPUT")
 
         for row in range(self.total_size):
             for wl_name in self.cell.get_all_wl_names():
-                self.add_pin("{0}_{1}".format(wl_name,row), "INPUT")
+                self.add_pin("{0}_{1}".format(wl_name, row), "INPUT")
 
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
-        self.replica_cell = factory.create(module_type="replica_bitcell")
+        self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell))
         self.add_mod(self.replica_cell)
-        self.dummy_cell = factory.create(module_type="dummy_bitcell")
+        self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
         self.add_mod(self.dummy_cell)
         try:
-            edge_module_type = ("col_cap_bitcell" if cell_properties.bitcell.end_caps else "dummy_bitcell")
+            edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy")
         except AttributeError:
-            edge_module_type = "dummy_bitcell"
+            edge_module_type = "dummy"
-        self.edge_cell = factory.create(module_type=edge_module_type)
+        self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
         self.add_mod(self.edge_cell)
         # Used for pin names only
         self.cell = factory.create(module_type="bitcell")
@@ -94,7 +95,7 @@ class replica_column(design.design):
             # Top/bottom cell are always dummy cells.
             # Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
             # Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
-            if (row>self.left_rbl and row<self.total_size-self.right_rbl-1):
+            if (row > self.left_rbl and row < self.total_size - self.right_rbl - 1):
                 self.cell_inst[row]=self.add_inst(name=name,
                                                   mod=self.replica_cell)
                 self.connect_inst(self.get_bitcell_pins(0, row))
@@ -118,7 +119,7 @@ class replica_column(design.design):
         from tech import cell_properties
         # Flip the mirrors if we have an odd number of replica+dummy rows at the bottom
         # so that we will start with mirroring rather than not mirroring
-        rbl_offset = (self.left_rbl+1)%2
+        rbl_offset = (self.left_rbl + 1) %2
 
         # if our bitcells are mirrored on the y axis, check if we are in global
         # column that needs to be flipped.
@@ -129,12 +130,10 @@ class replica_column(design.design):
             xoffset = self.replica_cell.width
 
         for row in range(self.total_size):
-            dir_x = False
+            # name = "bit_r{0}_{1}".format(row, "rbl")
-            name = "bit_r{0}_{1}".format(row,"rbl")
+            dir_x = cell_properties.bitcell.mirror.x and (row + rbl_offset) % 2
-            if cell_properties.bitcell.mirror.x and (row+rbl_offset)%2:
-                dir_x = True
 
-            offset = vector(xoffset,self.cell.height*(row+(row+rbl_offset)%2))
+            offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))
 
             if dir_x and dir_y:
                 dir_key = "XY"
@@ -174,9 +173,9 @@ class replica_column(design.design):
         for row in range(row_range_min, row_range_max):
             for wl_name in self.cell.get_all_wl_names():
                 wl_pin = self.cell_inst[row].get_pin(wl_name)
-                self.add_layout_pin(text="{0}_{1}".format(wl_name,row),
+                self.add_layout_pin(text="{0}_{1}".format(wl_name, row),
                                     layer=wl_pin.layer,
-                                    offset=wl_pin.ll().scale(0,1),
+                                    offset=wl_pin.ll().scale(0, 1),
                                     width=self.width,
                                     height=wl_pin.height())
 
@@ -194,10 +193,10 @@ class replica_column(design.design):
 
         pin_names = self.cell.get_all_bitline_names()
         for pin in pin_names:
-            bitcell_pins.append(pin+"_{0}".format(col))
+            bitcell_pins.append(pin + "_{0}".format(col))
         pin_names = self.cell.get_all_wl_names()
         for pin in pin_names:
-            bitcell_pins.append(pin+"_{0}".format(row))
+            bitcell_pins.append(pin + "_{0}".format(row))
         bitcell_pins.append("vdd")
         bitcell_pins.append("gnd")
 
@@ -211,12 +210,11 @@ class replica_column(design.design):
 
         pin_names = self.cell.get_all_bitline_names()
         for pin in pin_names:
-            bitcell_pins.append(pin+"_{0}".format(col))
+            bitcell_pins.append(pin + "_{0}".format(col))
         bitcell_pins.append("vdd")
 
         return bitcell_pins
 
-
     def exclude_all_but_replica(self):
         """Excludes all bits except the replica cell (self.replica_bit)."""
 

compiler/modules/row_cap_array.py

@@ -35,7 +35,7 @@ class row_cap_array(bitcell_base_array):
 
     def add_modules(self):
         """ Add the modules used in this design """
-        self.dummy_cell = factory.create(module_type="row_cap_bitcell_1rw_1r") # TODO: make module_type generic
+        self.dummy_cell = factory.create(module_type="row_cap_{}".format(OPTS.bitcell))
         self.add_mod(self.dummy_cell)
 
         self.cell = factory.create(module_type="bitcell")

compiler/options.py

@@ -124,26 +124,23 @@ class options(optparse.Values):
     purge_temp = True
 
     # These are the default modules that can be over-riden
+    bitcell_suffix = ""
     bank_select = "bank_select"
     bitcell_array = "bitcell_array"
     bitcell = "bitcell"
-    col_cap_bitcell = "col_cap_bitcell"
     column_mux_array = "single_level_column_mux_array"
     control_logic = "control_logic"
     decoder = "hierarchical_decoder"
     delay_chain = "delay_chain"
     dff_array = "dff_array"
     dff = "dff"
-    dummy_bitcell = "dummy_bitcell"
     inv_dec = "pinv"
     nand2_dec = "pnand2"
     nand3_dec = "pnand3"
     nand4_dec = "pnand4" # Not available right now
     precharge_array = "precharge_array"
     ptx = "ptx"
-    replica_bitcell = "replica_bitcell"
     replica_bitline = "replica_bitline"
-    row_cap_bitcell = "row_cap_bitcell"
     sense_amp_array = "sense_amp_array"
     sense_amp = "sense_amp"
     tri_gate_array = "tri_gate_array"

compiler/sram_factory.py

@@ -77,8 +77,8 @@ class sram_factory:
         """
         tech_module_type, tm_overridden = self.get_techmodule_type(module_type)
         user_module_type, um_overridden = self.get_usermodule_type(module_type)
-        #print(module_type, tech_module_type, tm_overridden)
+        # print(module_type, tech_module_type, tm_overridden)
-        #print(module_type, user_module_type, um_overridden)
+        # print(module_type, user_module_type, um_overridden)
         
         # overridden user modules have priority
         if um_overridden:

compiler/tests/04_single_level_column_mux_1rw_1r_test.py

@@ -22,10 +22,10 @@ class single_level_column_mux_1rw_1r_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(2, "Checking column mux port 0")
         tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")

compiler/tests/05_bitcell_1rw_1r_array_test.py

@@ -23,12 +23,10 @@ class bitcell_1rw_1r_array_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(2, "Testing 4x4 array for cell_1rw_1r")
         a = factory.create(module_type="bitcell_array", cols=4, rows=4)

compiler/tests/06_hierarchical_decoder_1rw_1r_test.py

@@ -23,10 +23,10 @@ class hierarchical_decoder_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
 
         # Use the 2 port cell since it is usually bigger/easier
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         # Checks 2x4 and 2-input NAND decoder
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")

compiler/tests/06_hierarchical_decoder_pbitcell_test.py

@@ -21,10 +21,10 @@ class hierarchical_decoder_pbitcell_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         # check hierarchical decoder for multi-port
-        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         factory.reset()
         debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")

compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py

@@ -22,11 +22,10 @@ class hierarchical_predecode2x4_1rw_1r_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        # Use the 2 port cell since it is usually bigger/easier
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = factory.create(module_type="hierarchical_predecode2x4")

compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py

@@ -22,10 +22,10 @@ class hierarchical_predecode2x4_pbitcell_test(openram_test):
         globals.init_openram(config_file)
 
         # checking hierarchical precode 2x4 for multi-port
-        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
         a = factory.create(module_type="hierarchical_predecode2x4")

compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py

@@ -23,10 +23,10 @@ class hierarchical_predecode3x8_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
 
         # Use the 2 port cell since it is usually bigger/easier
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")

compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py

@@ -22,10 +22,10 @@ class hierarchical_predecode3x8_pbitcell_test(openram_test):
         globals.init_openram(config_file)
 
         # checking hierarchical precode 3x8 for multi-port
-        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
         a = factory.create(module_type="hierarchical_predecode3x8")

compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py

@@ -20,10 +20,10 @@ class single_level_column_mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(1, "Testing sample for 4-way column_mux_array port 0")
         a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0")

compiler/tests/08_precharge_array_1rw_1r_test.py

@@ -22,10 +22,10 @@ class precharge_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         
         # check precharge array in multi-port
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
 
         factory.reset()
         debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)")

compiler/tests/08_wordline_driver_array_1rw_1r_test.py

@@ -23,10 +23,10 @@ class wordline_driver_array_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
 
         # Use the 2 port cell since it is usually bigger/easier
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")

compiler/tests/14_replica_bitcell_1rw_1r_array_test.py

@@ -19,21 +19,17 @@ class replica_bitcell_array_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
-        OPTS.col_cap_bitcell="col_cap_bitcell_1rw_1r"
-        OPTS.row_cap_bitcell="row_cap_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(2, "Testing 4x4 array for cell_1rw_1r")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0,1])
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1])
         self.local_check(a)
 
         debug.info(2, "Testing 4x4 array for cell_1rw_1r")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0,1])
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1])
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/18_port_address_1rw_1r_test.py

@@ -21,10 +21,10 @@ class port_address_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
 
         # Use the 2 port cell since it is usually bigger/easier
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(1, "Port address 16 rows")
         a = factory.create("port_address", cols=16, rows=16)

compiler/tests/18_port_data_1rw_1r_test.py

@@ -21,10 +21,10 @@ class port_data_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_1rw_1r_test.py

@@ -22,12 +22,10 @@ class single_bank_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_1w_1r_test.py

@@ -22,13 +22,10 @@ class single_bank_1w_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1w_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1w_1r"
-
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_wmask_1rw_1r_test.py

@@ -22,6 +22,10 @@ class single_bank_wmask_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
 
         c = sram_config(word_size=8,
                         write_size=4,

compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py

@@ -24,11 +24,10 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
         from sram_config import sram_config
 
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_psram_1bank_2mux_1w_1r_test.py

@@ -24,11 +24,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
         from sram_config import sram_config
 
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_psram_1bank_2mux_test.py

@@ -22,14 +22,12 @@ class psram_1bank_2mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
-        OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"        
         
-        # testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent)
+        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py

@@ -24,11 +24,10 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
         from sram_config import sram_config
 
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"        
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=64,

compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py

@@ -22,12 +22,10 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_sram_1bank_2mux_1w_1r_test.py

@@ -23,12 +23,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.replica_bitcell="replica_bitcell_1w_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1w_1r"
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py

@@ -22,12 +22,10 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=2,
                         num_words=128,

compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py

@@ -22,12 +22,10 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16,

compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py

@@ -24,12 +24,10 @@ class psram_1bank_nomux_func_test(openram_test):
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload

compiler/tests/22_sram_wmask_1w_1r_func_test.py

@@ -26,13 +26,10 @@ class sram_wmask_1w_1r_func_test(openram_test):
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1w_1r"
-        OPTS.dummy_bitcell = "dummy_bitcell_1w_1r"
-
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload