Auto-generate port dependent cell names.

2026-08-29 17:39:02 +02:00 · 2020-06-05 15:09:22 -07:00
parent 00b51f5464
commit 5514996708
34 changed files with 82 additions and 121 deletions
@@ -35,7 +35,7 @@ class row_cap_array(bitcell_base_array):

    def add_modules(self):
        """ Add the modules used in this design """
-        self.dummy_cell = factory.create(module_type="row_cap_bitcell_1rw_1r") # TODO: make module_type generic
+        self.dummy_cell = factory.create(module_type="row_cap_{}".format(OPTS.bitcell))
        self.add_mod(self.dummy_cell)

        self.cell = factory.create(module_type="bitcell")