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Auto-generate port dependent cell names.

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This commit is contained in:
mrg
2020-06-05 15:09:22 -07:00
parent 00b51f5464
commit 5514996708
34 changed files with 82 additions and 121 deletions
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compiler/modules/col_cap_array.py
+2 -2
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@@ -8,6 +8,7 @@ from sram_factory import factory
from globals import OPTS
from tech import cell_properties
class col_cap_array(bitcell_base_array):
"""
Generate a dummy row/column for the replica array.
@@ -35,8 +36,7 @@ class col_cap_array(bitcell_base_array):
def add_modules(self):
""" Add the modules used in this design """
# self.dummy_cell = factory.create(module_type="col_cap_bitcell_1rw_1r") # TODO: make module_type generic
self.dummy_cell = factory.create(module_type="col_cap_bitcell")
self.dummy_cell = factory.create(module_type="col_cap_{}".format(OPTS.bitcell))
self.add_mod(self.dummy_cell)
self.cell = factory.create(module_type="bitcell")