luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

PEP8 cleanup. DRC/LVS returns errors.

This commit is contained in:
mrg 2020-04-02 09:47:39 -07:00
parent 0d6c84036d
commit 5349323acd
3 changed files with 75 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
compiler/base/hierarchy_design.py
View File

@ -40,18 +40,17 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
inst_map = inst.mod.pin_map inst_map = inst.mod.pin_map
return inst_map return inst_map
def DRC_LVS(self, final_verification=False, force_check=False):
def DRC_LVS(self, final_verification=False, top_level=False):
"""Checks both DRC and LVS for a module""" """Checks both DRC and LVS for a module"""
# Final verification option does not allow nets to be connected by label. # Final verification option does not allow nets to be connected by label.
# Unit tests will check themselves. # Unit tests will check themselves.
if OPTS.is_unit_test: if not force_check and OPTS.is_unit_test:
return ("skipped", "skipped") return ("skipped", "skipped")
if not OPTS.check_lvsdrc: if not force_check and not OPTS.check_lvsdrc:
return ("skipped", "skipped") return ("skipped", "skipped")
# Do not run if disabled in options. # Do not run if disabled in options.
if (OPTS.inline_lvsdrc or top_level): if (OPTS.inline_lvsdrc or force_check):
tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name)
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
@ -60,8 +59,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification)
num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors)) debug.check(num_drc_errors == 0,
debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors)) "DRC failed for {0} with {1} error(s)".format(self.name,
num_drc_errors))
debug.check(num_lvs_errors == 0,
"LVS failed for {0} with {1} errors(s)".format(self.name,
num_lvs_errors))
os.remove(tempspice) os.remove(tempspice)
os.remove(tempgds) os.remove(tempgds)
@ -77,7 +80,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
self.gds_write(tempgds) self.gds_write(tempgds)
num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification) num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification)
debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error)) debug.check(num_errors == 0,
"DRC failed for {0} with {1} error(s)".format(self.name,
num_errors))
os.remove(tempgds) os.remove(tempgds)
@ -96,7 +101,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
self.sp_write(tempspice) self.sp_write(tempspice)
self.gds_write(tempgds) self.gds_write(tempgds)
num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors)) debug.check(num_errors == 0,
"LVS failed for {0} with {1} error(s)".format(self.name,
num_errors))
os.remove(tempspice) os.remove(tempspice)
os.remove(tempgds) os.remove(tempgds)
@ -114,7 +121,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# Translate port names to external nets # Translate port names to external nets
if len(port_nets) != len(self.pins): if len(port_nets) != len(self.pins):
debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1) debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,
self.pins),
1)
port_dict = {pin: port for pin, port in zip(self.pins, port_nets)} port_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
debug.info(3, "Instance name={}".format(inst_name)) debug.info(3, "Instance name={}".format(inst_name))
for subinst, conns in zip(self.insts, self.conns): for subinst, conns in zip(self.insts, self.conns):
@ -128,7 +137,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
"""Collects all the nets and the parent inst of that net.""" """Collects all the nets and the parent inst of that net."""
# Translate port names to external nets # Translate port names to external nets
if len(port_nets) != len(self.pins): if len(port_nets) != len(self.pins):
debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1) debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,
self.pins),
1)
port_dict = {pin: port for pin, port in zip(self.pins, port_nets)} port_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
debug.info(3, "Instance name={}".format(inst_name)) debug.info(3, "Instance name={}".format(inst_name))
for subinst, conns in zip(self.insts, self.conns): for subinst, conns in zip(self.insts, self.conns):
@ -188,8 +199,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
parent_net.lower() == alias_net.lower() parent_net.lower() == alias_net.lower()
def get_mod_net(self, parent_net, child_inst, child_conns): def get_mod_net(self, parent_net, child_inst, child_conns):
"""Given an instance and net, returns the internal net in the mod """
corresponding to input net.""" Given an instance and net, returns the internal net in the mod
corresponding to input net.
"""
for conn, pin in zip(child_conns, child_inst.mod.pins): for conn, pin in zip(child_conns, child_inst.mod.pins):
if parent_net.lower() == conn.lower(): if parent_net.lower() == conn.lower():
return pin return pin

16
compiler/modules/hierarchical_decoder.py
View File

@ -37,13 +37,19 @@ class hierarchical_decoder(design.design):
def find_decoder_height(self): def find_decoder_height(self):
b = factory.create(module_type="bitcell") b = factory.create(module_type="bitcell")
cell_height = b.height return (b.height, 1)
cell_multiple = 1
while cell_multiple < 3:
cell_height = cell_multiple * b.height
and3 = factory.create(module_type="pand3", and3 = factory.create(module_type="pand3",
height=cell_height) height=cell_height)
(drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True)
# Try to make a nand with a given height if drc_errors + lvs_errors == 0:
# Default return (cell_height, cell_multiple)
return (b.height, 1) cell_multiple += 1
else:
debug.error("Couldn't find a valid decoder height multiple.", -1)
def create_netlist(self): def create_netlist(self):
self.add_modules() self.add_modules()

2
compiler/sram/sram_base.py
View File

@ -121,7 +121,7 @@ class sram_base(design, verilog, lef):
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
# We only enable final verification if we have routed the design # We only enable final verification if we have routed the design
self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) self.DRC_LVS(final_verification=OPTS.route_supplies, roce_check=True)
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Verification", datetime.datetime.now(), start_time) print_time("Verification", datetime.datetime.now(), start_time)