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https://github.com/VLSIDA/OpenRAM.git
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Output functional stimulus to output directory.
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@@ -21,13 +21,24 @@ class functional(simulation):
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for successful SRAM operation.
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"""
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def __init__(self, sram, spfile, corner, cycles=15):
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def __init__(self, sram, spfile, corner=None, cycles=15, period=None, output_path=None):
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super().__init__(sram, spfile, corner)
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# Seed the characterizer with a constant seed for unit tests
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if OPTS.is_unit_test:
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random.seed(12345)
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if not corner:
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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if period:
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self.period = period
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if not output_path:
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self.output_path = OPTS.openram_temp
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else:
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self.output_path = output_path
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if self.write_size:
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self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
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else:
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@@ -58,15 +69,14 @@ class functional(simulation):
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self.read_check = []
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self.read_results = []
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def run(self, feasible_period=None):
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if feasible_period: # period defaults to tech.py feasible period otherwise.
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self.period = feasible_period
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# Generate a random sequence of reads and writes
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self.create_random_memory_sequence()
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# Run SPICE simulation
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# Write SPICE simulation
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self.write_functional_stimulus()
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self.stim.run_sim()
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def run(self):
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self.stim.run_sim(self.stim_sp)
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# read dout values from SPICE simulation. If the values do not fall within the noise margins, return the error.
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(success, error) = self.read_stim_results()
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@@ -330,7 +340,8 @@ class functional(simulation):
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def write_functional_stimulus(self):
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""" Writes SPICE stimulus. """
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.stim_sp = "functional_stim.sp"
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temp_stim = "{0}/{1}".format(self.output_path, self.stim_sp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Functional test stimulus file for {}ns period\n\n".format(self.period))
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self.stim = stimuli(self.sf, self.corner)
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