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Disable perimeter pins and make an option

This commit is contained in:
mrg 2020-06-14 16:44:10 -07:00
parent 78be9f367a
commit 52ee7b0a19
2 changed files with 78 additions and 56 deletions
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4
compiler/options.py
View File

@ -123,6 +123,10 @@ class options(optparse.Values):
analytical_delay = True analytical_delay = True
# Purge the temp directory after a successful # Purge the temp directory after a successful
# run (doesn't purge on errors, anyhow) # run (doesn't purge on errors, anyhow)
# Route the input/output pins to the perimeter
perimeter_pins = False
purge_temp = True purge_temp = True
# These are the default modules that can be over-riden # These are the default modules that can be over-riden

130
compiler/sram/sram_1bank.py
View File

@ -9,7 +9,7 @@ import debug
from vector import vector from vector import vector
from sram_base import sram_base from sram_base import sram_base
from contact import m2_via from contact import m2_via
from globals import OPTS
class sram_1bank(sram_base): class sram_1bank(sram_base):
""" """
@ -246,7 +246,6 @@ class sram_1bank(sram_base):
""" """
Add the top-level pins for a single bank SRAM with control. Add the top-level pins for a single bank SRAM with control.
""" """
highest_coord = self.find_highest_coords() highest_coord = self.find_highest_coords()
lowest_coord = self.find_lowest_coords() lowest_coord = self.find_lowest_coords()
bbox = [lowest_coord, highest_coord] bbox = [lowest_coord, highest_coord]
@ -263,83 +262,102 @@ class sram_1bank(sram_base):
for signal in self.control_logic_inputs[port]: for signal in self.control_logic_inputs[port]:
if signal == "clk": if signal == "clk":
continue continue
self.add_perimeter_pin(name=signal + "{}".format(port), if OPTS.perimeter_pins:
pin=self.control_logic_insts[port].get_pin(signal), self.add_perimeter_pin(name=signal + "{}".format(port),
side=left_or_right, pin=self.control_logic_insts[port].get_pin(signal),
bbox=bbox) side=left_or_right,
# self.copy_layout_pin(self.control_logic_insts[port], bbox=bbox)
# signal, else:
# signal + "{}".format(port)) self.copy_layout_pin(self.control_logic_insts[port],
signal,
signal + "{}".format(port))
self.add_perimeter_pin(name="clk{}".format(port), if OPTS.perimeter_pins:
pin=self.control_logic_insts[port].get_pin("clk"), self.add_perimeter_pin(name="clk{}".format(port),
side=bottom_or_top, pin=self.control_logic_insts[port].get_pin("clk"),
bbox=bbox) side=bottom_or_top,
bbox=bbox)
else:
self.copy_layout_pin(self.control_logic_insts[port],
"clk",
"clk{}".format(port))
# Data output pins go to BOTTOM/TOP # Data output pins go to BOTTOM/TOP
if port in self.read_ports: if port in self.read_ports:
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit), if OPTS.perimeter_pins:
pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)), self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit),
side=bottom_or_top, pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)),
bbox=bbox) side=bottom_or_top,
# self.copy_layout_pin(self.bank_inst, bbox=bbox)
# "dout{0}_{1}".format(port, bit), else:
# "dout{0}[{1}]".format(port, bit)) self.copy_layout_pin(self.bank_inst,
"dout{0}_{1}".format(port, bit),
"dout{0}[{1}]".format(port, bit))
# Lower address bits go to BOTTOM/TOP # Lower address bits go to BOTTOM/TOP
for bit in range(self.col_addr_size): for bit in range(self.col_addr_size):
self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit), if OPTS.perimeter_pins:
pin=self.col_addr_dff_insts[port].get_pin("din_{}".format(bit)), self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit),
side=bottom_or_top, pin=self.col_addr_dff_insts[port].get_pin("din_{}".format(bit)),
bbox=bbox) side=bottom_or_top,
# self.copy_layout_pin(self.col_addr_dff_insts[port], bbox=bbox)
# "din_{}".format(bit), else:
# "addr{0}[{1}]".format(port, bit)) self.copy_layout_pin(self.col_addr_dff_insts[port],
"din_{}".format(bit),
"addr{0}[{1}]".format(port, bit))
# Upper address bits go to LEFT/RIGHT # Upper address bits go to LEFT/RIGHT
for bit in range(self.row_addr_size): for bit in range(self.row_addr_size):
self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit + self.col_addr_size), if OPTS.perimeter_pins:
pin=self.row_addr_dff_insts[port].get_pin("din_{}".format(bit)), self.add_perimeter_pin(name="addr{0}[{1}]".format(port, bit + self.col_addr_size),
side=left_or_right, pin=self.row_addr_dff_insts[port].get_pin("din_{}".format(bit)),
bbox=bbox) side=left_or_right,
# self.copy_layout_pin(self.row_addr_dff_insts[port], bbox=bbox)
# "din_{}".format(bit), else:
# "addr{0}[{1}]".format(port, bit + self.col_addr_size)) self.copy_layout_pin(self.row_addr_dff_insts[port],
"din_{}".format(bit),
"addr{0}[{1}]".format(port, bit + self.col_addr_size))
# Data input pins go to BOTTOM/TOP # Data input pins go to BOTTOM/TOP
if port in self.write_ports: if port in self.write_ports:
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit), if OPTS.perimeter_pins:
pin=self.data_dff_insts[port].get_pin("din_{}".format(bit)), self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit),
side=bottom_or_top, pin=self.data_dff_insts[port].get_pin("din_{}".format(bit)),
bbox=bbox) side=bottom_or_top,
# self.copy_layout_pin(self.data_dff_insts[port], bbox=bbox)
# "din_{}".format(bit), else:
# "din{0}[{1}]".format(port, bit)) self.copy_layout_pin(self.data_dff_insts[port],
"din_{}".format(bit),
"din{0}[{1}]".format(port, bit))
# Write mask pins go to BOTTOM/TOP # Write mask pins go to BOTTOM/TOP
if port in self.write_ports: if port in self.write_ports:
if self.write_size: if self.write_size:
for bit in range(self.num_wmasks): for bit in range(self.num_wmasks):
self.add_perimeter_pin(name="wmask{0}[{1}]".format(port, bit), if OPTS.perimeter_pins:
pin=self.wmask_dff_insts[port].get_pin("din_{}".format(bit)), self.add_perimeter_pin(name="wmask{0}[{1}]".format(port, bit),
side=bottom_or_top, pin=self.wmask_dff_insts[port].get_pin("din_{}".format(bit)),
bbox=bbox) side=bottom_or_top,
# self.copy_layout_pin(self.wmask_dff_insts[port], bbox=bbox)
# "din_{}".format(bit), else:
# "wmask{0}[{1}]".format(port, bit)) self.copy_layout_pin(self.wmask_dff_insts[port],
"din_{}".format(bit),
"wmask{0}[{1}]".format(port, bit))
# Spare wen pins go to BOTTOM/TOP # Spare wen pins go to BOTTOM/TOP
if port in self.write_ports: if port in self.write_ports:
for bit in range(self.num_spare_cols): for bit in range(self.num_spare_cols):
self.add_perimeter_pin(name="spare_wen{0}[{1}]".format(port, bit), if OPTS.perimeter_pins:
pin=self.spare_wen_dff_insts[port].get_pin("din_{}".format(bit)), self.add_perimeter_pin(name="spare_wen{0}[{1}]".format(port, bit),
side=left_or_right, pin=self.spare_wen_dff_insts[port].get_pin("din_{}".format(bit)),
bbox=bbox) side=left_or_right,
# self.copy_layout_pin(self.spare_wen_dff_insts[port], bbox=bbox)
# "din_{}".format(bit), else:
# "spare_wen{0}[{1}]".format(port, bit)) self.copy_layout_pin(self.spare_wen_dff_insts[port],
"din_{}".format(bit),
"spare_wen{0}[{1}]".format(port, bit))
def route_layout(self): def route_layout(self):
""" Route a single bank SRAM """ """ Route a single bank SRAM """