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Merge branch 'dev' into pdriver

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Jennifer Eve Sowash 2018-11-26 13:15:47 -08:00
parent bb7773ca7f 21fec02dc7
commit 524334d24d
39 changed files with 929 additions and 893 deletions
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14
.coveragerc Normal file
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@ -0,0 +1,14 @@
[run]
omit =
# omit anything in a .local directory anywhere
*/.local/*
# omit everything in /usr
/usr/*
[paths]
source =
/home/gitlab-runner/builds/2fd64746/0
/home/gitlab-runner/builds/2fd64746/1
/home/gitlab-runner/builds/2fd64746/2
/home/gitlab-runner/builds/2fd64746/3
/home/gitlab-runner/builds/2fd64746/4
/home/gitlab-runner/builds/2fd64746/5

37
.gitlab-ci.yml
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@ -1,6 +1,39 @@
before_script:
- . /home/gitlab-runner/setup-paths.sh
- export OPENRAM_HOME="`pwd`/compiler"
- export OPENRAM_TECH="`pwd`/technology"
stages:
- test
- coverage
freepdk45: freepdk45:
script: "/home/gitlab-runner/regress_freepdk45.sh" stage: test
script:
- coverage run -p $OPENRAM_HOME/tests/regress.py -t freepdk45
artifacts:
paths:
- .coverage.*
expire_in: 1 week
scn4m_subm: scn4m_subm:
script: "/home/gitlab-runner/regress_scn4m_subm.sh" stage: test
script:
- coverage run -p $OPENRAM_HOME/tests/regress.py -t scn4m_subm
artifacts:
paths:
- .coverage.*
expire_in: 1 week
coverage:
stage: coverage
script:
- coverage combine
- coverage report
- coverage html -d coverage_html
artifacts:
paths:
- coverage_html
expire_in: 1 week
coverage: '/TOTAL.+ ([0-9]{1,3}%)/'

20
CONTRIBUTING.md
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@ -7,6 +7,26 @@ list at openram-dev-group@ucsc.edu. We are happy to give insights into
the best way to implement a change to ensure your contribution will be the best way to implement a change to ensure your contribution will be
accepted and help other OpenRAM users. accepted and help other OpenRAM users.
# Directory Structure
* compiler - openram compiler itself (pointed to by OPENRAM_HOME)
* compiler/base - base data structure modules
* compiler/pgates - parameterized cells (e.g. logic gates)
* compiler/bitcells - various bitcell styles
* compiler/modules - high-level modules (e.g. decoders, etc.)
* compiler/verify - DRC and LVS verification wrappers
* compiler/characterizer - timing characterization code
* compiler/gdsMill - GDSII reader/writer
* compiler/router - router for signals and power supplies
* compiler/tests - unit tests
* technology - openram technology directory (pointed to by OPENRAM_TECH)
* technology/freepdk45 - example configuration library for [FreePDK45 technology node
* technology/scn4m_subm - example configuration library [SCMOS] technology node
* technology/scn3me_subm - unsupported configuration (not enough metal layers)
* technology/setup_scripts - setup scripts to customize your PDKs and OpenRAM technologies
* docs - LaTeX manual (outdated)
* lib - IP library of pregenerated memories
# Code Style # Code Style
Our code may not be the best and we acknowledge that. We welcome Our code may not be the best and we acknowledge that. We welcome

196
README.md
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@ -1,83 +1,119 @@
# OpenRAM # OpenRAM
[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits)
[![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) [![Python 3.5](https://img.shields.io/badge/Python-3.5-green.svg)](https://www.python.org/)
[![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE)
Master:
[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master)
![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)
[![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip)
Dev:
[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev)
![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)
[![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip)
An open-source static random access memory (SRAM) compiler. An open-source static random access memory (SRAM) compiler.
# Why OpenRAM? # What is OpenRAM?
<img align="right" width="25%" src="images/SCMOS_16kb_sram.jpg">
OpenRAM is an open-source Python framework to create the layout,
netlists, timing and power models, placement and routing models, and
other views necessary to use SRAMs in ASIC design. OpenRAM supports
integration in both commercial and open-source flows with both
predictive and fabricable technologies.
# Basic Setup # Basic Setup
The OpenRAM compiler has very few dependencies: The OpenRAM compiler has very few dependencies:
+ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) + [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
+ Python 3.5 and higher + Python 3.5 or higher
+ Python numpy (pip3 install numpy to install) + Python numpy (pip3 install numpy to install)
+ flask_table (pip3 install flask to install) + flask_table (pip3 install flask to install)
If you want to perform DRC and LVS, you will need either: If you want to perform DRC and LVS, you will need either:
+ Calibre (for [FreePDK45] or [SCMOS]) + Calibre (for [FreePDK45])
+ [Magic] + [Netgen] (for [SCMOS] only) + [Magic] + [Netgen] (for [SCMOS])
You must set two environment variables:
+ OPENRAM\_HOME should point to the compiler source directory.
+ OPENERAM\_TECH should point to a root technology directory.
For example add this to your .bashrc:
You must set two environment variables: OPENRAM\_HOME should point to
the compiler source directory. OPENERAM\_TECH should point to a root
technology directory that contains subdirs of all other technologies.
For example, in bash, add to your .bashrc:
``` ```
export OPENRAM_HOME="$HOME/openram/compiler" export OPENRAM_HOME="$HOME/openram/compiler"
export OPENRAM_TECH="$HOME/openram/technology" export OPENRAM_TECH="$HOME/openram/technology"
``` ```
For example, in csh/tcsh, add to your .cshrc/.tcshrc:
You may also wish to add OPENRAM\_HOME to your PYTHONPATH:
``` ```
setenv OPENRAM_HOME "$HOME/openram/compiler" export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME"
setenv OPENRAM_TECH "$HOME/openram/technology"
``` ```
We include the tech files necessary for [FreePDK45] and [SCMOS]. The [SCMOS] We include the tech files necessary for [FreePDK45] and [SCMOS]
spice models, however, are generic and should be replaced with foundry SCN4M_SUBM. The [SCMOS] spice models, however, are generic and should
models. be replaced with foundry models. If you are using [FreePDK45], you
If you are using [FreePDK45], you should also have that set up and have the should also have that set up and have the environment variable point
environment variable point to the PDK. to the PDK. For example add this to your .bashrc:
For example, in bash, add to your .bashrc:
``` ```
export FREEPDK45="/bsoe/software/design-kits/FreePDK45" export FREEPDK45="/bsoe/software/design-kits/FreePDK45"
``` ```
For example, in csh/tcsh, add to your .tcshrc:
```
setenv FREEPDK45 "/bsoe/software/design-kits/FreePDK45"
```
We do not distribute the PDK, but you may download [FreePDK45]
You may get the entire [FreePDK45 PDK here][FreePDK45].
If you are using [SCMOS], you should install [Magic] and [Netgen]. If you are using [SCMOS], you should install [Magic] and [Netgen].
We have included the SCN4M design rules from [Qflow]. We have included the most recent SCN4M_SUBM design rules from [Qflow].
# Directory Structure # Basic Usage
* compiler - openram compiler itself (pointed to by OPENRAM_HOME) Once you have defined the environment, you can run OpenRAM from the command line
* compiler/base - base data structure modules using a single configuration file written in Python.
* compiler/pgates - parameterized cells (e.g. logic gates)
* compiler/bitcells - various bitcell styles For example, create a file called *myconfig.py* specifying the following
* compiler/modules - high-level modules (e.g. decoders, etc.) parameters for your memory:
* compiler/verify - DRC and LVS verification wrappers
* compiler/characterizer - timing characterization code ```
* compiler/gdsMill - GDSII reader/writer # Data word size
* compiler/router - router for signals and power supplies word_size = 2
* compiler/tests - unit tests # Number of words in the memory
* technology - openram technology directory (pointed to by OPENRAM_TECH) num_words = 16
* technology/freepdk45 - example configuration library for [FreePDK45 technology node
* technology/scn4m_subm - example configuration library [SCMOS] technology node # Technology to use in $OPENRAM_TECH
* technology/scn3me_subm - unsupported configuration (not enough metal layers) tech_name = "scn4m_subm"
* technology/setup_scripts - setup scripts to customize your PDKs and OpenRAM technologies # Process corners to characterize
* docs - LaTeX manual (outdated) process_corners = ["TT"]
* lib - IP library of pregenerated memories # Voltage corners to characterize
supply_voltages = [ 3.3 ]
# Temperature corners to characterize
temperatures = [ 25 ]
# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
# Disable analytical models for full characterization (WARNING: slow!)
# analytical_delay = False
```
You can then run OpenRAM by executing:
```
python3 $OPENRAM_HOME/openram.py myconfig
```
You can see all of the options for the configuration file in
$OPENRAM\_HOME/options.py
# Unit Tests # Unit Tests
Regression testing performs a number of tests for all modules in OpenRAM. Regression testing performs a number of tests for all modules in OpenRAM.
From the unit test directory ($OPENRAM\_HOME/tests),
use the following command to run all regression tests:
Use the command:
``` ```
python3 regress.py python3 regress.py
``` ```
@ -96,68 +132,100 @@ To specify a particular technology use "-t <techname>" such as
The default for openram.py is specified in the configuration file. The default for openram.py is specified in the configuration file.
# Creating Custom Technologies # Porting to a New Technology
If you want to support a enw technology, you will need to create: If you want to support a enw technology, you will need to create:
+ a setup script for each technology you want to use + a setup script for each technology you want to use
+ a technology directory for each technology with the base cells + a technology directory for each technology with the base cells
All setup scripts should be in the setup\_scripts directory under the All setup scripts should be in the setup\_scripts directory under the
$OPENRAM\_TECH directory. We provide two technology examples for [SCMOS] and [FreePDK45]. $OPENRAM\_TECH directory. We provide two technology examples for
Please look at the following file for an example of what is needed for OpenRAM: [SCMOS] and [FreePDK45]. Please look at the following file for an
example of what is needed for OpenRAM:
``` ```
$OPENRAM_TECH/setup_scripts/setup_openram_freepdk45.py $OPENRAM_TECH/setup_scripts/setup_openram_freepdk45.py
``` ```
Each setup script should be named as: setup\_openram\_{tech name}.py. Each setup script should be named as: setup\_openram\_{tech name}.py.
Each specific technology (e.g., [FreePDK45]) should be a subdirectory Each specific technology (e.g., [FreePDK45]) should be a subdirectory
(e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files: (e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files:
1. gds_lib folder with all the .gds (premade) library cells. At a * gds_lib folder with all the .gds (premade) library cells:
minimum this includes: * dff.gds
* ms_flop.gds
* sense_amp.gds * sense_amp.gds
* write_driver.gds * write_driver.gds
* cell_6t.gds * cell_6t.gds
* replica_cell_6t.gds * replica\_cell\_6t.gds
* tri_gate.gds * sp_lib folder with all the .sp (premade) library netlists for the above cells.
2. sp_lib folder with all the .sp (premade) library netlists for the above cells. * layers.map
3. layers.map * A valid tech Python module (tech directory with __init__.py and tech.py) with:
4. A valid tech Python module (tech directory with __init__.py and tech.py) with:
* References in tech.py to spice models * References in tech.py to spice models
* DRC/LVS rules needed for dynamic cells and routing * DRC/LVS rules needed for dynamic cells and routing
* Layer information * Layer information
* Spice and supply information
* etc. * etc.
# Get Involved # Get Involved
+ Report bugs by submitting a [Github issue]. + Report bugs by submitting [Github issues].
+ Develop new features (see [how to contribute](./CONTRIBUTING.md)) + Develop new features (see [how to contribute](./CONTRIBUTING.md))
+ Submit code/fixes using a [Github pull request] + Submit code/fixes using a [Github pull request]
+ Follow our [project][Github projects]. + Follow our [project][Github projects].
+ Read and cite our [ICCAD paper][OpenRAMpaper] + Read and cite our [ICCAD paper][OpenRAMpaper]
# Further Help
+ [Additional hints](./HINTS.md)
+ [OpenRAM Slack Workspace][Slack]
+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
# License # License
OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
# Contributors & Acknowledgment # Contributors & Acknowledgment
- [Matthew Guthaus][Matthew Guthaus] created the OpenRAM project and is the lead architect. - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
- [James Stine] from [VLSIARCH] co-founded the project.
- Hunter Nichols maintains and updates the timing characterization.
- Michael Grimes created and maintains the multiport netlist code.
- Jennifer Sowash is creating the OpenRAM IP library.
- Jesse Cirimelli-Low created the datasheet generation.
- Samira Ataei created early multi-bank layouts and control logic.
- Bin Wu created early parameterized cells.
- Yusu Wang is porting parameterized cells to new technologies.
- Brian Chen created early prototypes of the timing characterizer.
- Jeff Butera created early prototypes of the bank layout.
If I forgot to add you, please let me know!
* * * * * *
[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg [Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg
[Github issues]: https://github.com/PrivateRAM/PrivateRAM/issues [James Stine]: https://ece.okstate.edu/content/stine-james-e-jr-phd
[Github pull request]: https://github.com/PrivateRAM/PrivateRAM/pulls
[Github projects]: https://github.com/PrivateRAM/PrivateRAM/projects
[email me]: mailto:mrg+openram@ucsc.edu
[VLSIDA]: https://vlsida.soe.ucsc.edu [VLSIDA]: https://vlsida.soe.ucsc.edu
[OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/ [VLSIARCH]: https://vlsiarch.ecen.okstate.edu/
[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/
[Github issues]: https://github.com/VLSIDA/PrivateRAM/issues
[Github pull request]: https://github.com/VLSIDA/PrivateRAM/pulls
[Github projects]: https://github.com/VLSIDA/PrivateRAM/projects
[email me]: mailto:mrg+openram@ucsc.edu
[dev-group]: mailto:openram-dev-group@ucsc.edu
[user-group]: mailto:openram-user-group@ucsc.edu
[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu
[user-group-subscribe]: mailto:openram-user-group+subscribe@ucsc.edu
[Magic]: http://opencircuitdesign.com/magic/ [Magic]: http://opencircuitdesign.com/magic/
[Netgen]: http://opencircuitdesign.com/netgen/ [Netgen]: http://opencircuitdesign.com/netgen/
[Qflow]: http://opencircuitdesign.com/qflow/history.html [Qflow]: http://opencircuitdesign.com/qflow/history.html
[Ngspice]: http://ngspice.sourceforge.net/
[OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/
[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents [FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf [SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf
[Ngspice]: http://ngspice.sourceforge.net/
[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/ [Slack]: https://join.slack.com/t/openram/shared_invite/enQtNDgxMjc3NzU5NTI1LTE4ODMyM2I0Mzk2ZmFiMjgwYTYyMTQ4NTgwMmUwMDhiM2E1MDViNDRjYzU1NjJhZTQxNWZjMzE3M2FlODBmZjA

2
compiler/base/contact.py
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@ -172,5 +172,5 @@ active = contact(layer_stack=("active", "contact", "poly"))
poly = contact(layer_stack=("poly", "contact", "metal1")) poly = contact(layer_stack=("poly", "contact", "metal1"))
m1m2 = contact(layer_stack=("metal1", "via1", "metal2")) m1m2 = contact(layer_stack=("metal1", "via1", "metal2"))
m2m3 = contact(layer_stack=("metal2", "via2", "metal3")) m2m3 = contact(layer_stack=("metal2", "via2", "metal3"))
#m3m4 = contact(layer_stack=("metal3", "via3", "metal4")) m3m4 = contact(layer_stack=("metal3", "via3", "metal4"))

12
compiler/base/design.py
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@ -22,9 +22,7 @@ class design(hierarchy_design):
self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space) self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space) self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space)
# SCMOS doesn't have m4... self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space)
#self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space)
self.m3_pitch = self.m2_pitch
def setup_drc_constants(self): def setup_drc_constants(self):
""" These are some DRC constants used in many places in the compiler.""" """ These are some DRC constants used in many places in the compiler."""
@ -38,6 +36,8 @@ class design(hierarchy_design):
self.m2_space = drc("metal2_to_metal2") self.m2_space = drc("metal2_to_metal2")
self.m3_width = drc("minwidth_metal3") self.m3_width = drc("minwidth_metal3")
self.m3_space = drc("metal3_to_metal3") self.m3_space = drc("metal3_to_metal3")
self.m4_width = drc("minwidth_metal4")
self.m4_space = drc("metal4_to_metal4")
self.active_width = drc("minwidth_active") self.active_width = drc("minwidth_active")
self.active_space = drc("active_to_body_active") self.active_space = drc("active_to_body_active")
self.contact_width = drc("minwidth_contact") self.contact_width = drc("minwidth_contact")
@ -65,8 +65,12 @@ class design(hierarchy_design):
self.readwrite_ports = [] self.readwrite_ports = []
# These are the read/write and write-only port indices # These are the read/write and write-only port indices
self.write_ports = [] self.write_ports = []
# These are the write-only port indices.
self.writeonly_ports = []
# These are teh read/write and read-only port indice # These are teh read/write and read-only port indice
self.read_ports = [] self.read_ports = []
# These are the read-only port indices.
self.readonly_ports = []
# These are all the ports # These are all the ports
self.all_ports = list(range(total_ports)) self.all_ports = list(range(total_ports))
@ -78,9 +82,11 @@ class design(hierarchy_design):
port_number += 1 port_number += 1
for port in range(OPTS.num_w_ports): for port in range(OPTS.num_w_ports):
self.write_ports.append(port_number) self.write_ports.append(port_number)
self.writeonly_ports.append(port_number)
port_number += 1 port_number += 1
for port in range(OPTS.num_r_ports): for port in range(OPTS.num_r_ports):
self.read_ports.append(port_number) self.read_ports.append(port_number)
self.readonly_ports.append(port_number)
port_number += 1 port_number += 1
def analytical_power(self, proc, vdd, temp, load): def analytical_power(self, proc, vdd, temp, load):

3
compiler/base/geometry.py
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@ -200,18 +200,19 @@ class instance(geometry):
self.mod.gds_write_file(self.gds) self.mod.gds_write_file(self.gds)
# now write an instance of my module/structure # now write an instance of my module/structure
new_layout.addInstance(self.gds, new_layout.addInstance(self.gds,
self.mod.name,
offsetInMicrons=self.offset, offsetInMicrons=self.offset,
mirror=self.mirror, mirror=self.mirror,
rotate=self.rotate) rotate=self.rotate)
def place(self, offset, mirror="R0", rotate=0): def place(self, offset, mirror="R0", rotate=0):
""" This updates the placement of an instance. """ """ This updates the placement of an instance. """
debug.info(3, "placing instance {}".format(self.name))
# Update the placement of an already added instance # Update the placement of an already added instance
self.offset = vector(offset).snap_to_grid() self.offset = vector(offset).snap_to_grid()
self.mirror = mirror self.mirror = mirror
self.rotate = rotate self.rotate = rotate
self.update_boundary() self.update_boundary()
debug.info(3, "placing instance {}".format(self))
def get_pin(self,name,index=-1): def get_pin(self,name,index=-1):

18
compiler/base/hierarchy_design.py
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@ -34,20 +34,24 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# because each reference must be a unique name. # because each reference must be a unique name.
# These modules ensure unique names or have no changes if they # These modules ensure unique names or have no changes if they
# aren't unique # aren't unique
ok_list = ['ms_flop', ok_list = ['contact',
'dff',
'dff_buf',
'bitcell',
'contact',
'ptx', 'ptx',
'pbitcell',
'replica_pbitcell',
'sram', 'sram',
'hierarchical_predecode2x4', 'hierarchical_predecode2x4',
'hierarchical_predecode3x8'] 'hierarchical_predecode3x8']
if name not in hierarchy_design.name_map:
# Library cells don't change
if self.is_library_cell:
return
# Name is unique so far
elif name not in hierarchy_design.name_map:
hierarchy_design.name_map.append(name) hierarchy_design.name_map.append(name)
else: else:
# Name is in our list of exceptions (they don't change)
for ok_names in ok_list: for ok_names in ok_list:
if ok_names in self.__class__.__name__: if ok_names == self.__class__.__name__:
break break
else: else:
debug.error("Duplicate layout reference name {0} of class {1}. GDS2 requires names be unique.".format(name,self.__class__),-1) debug.error("Duplicate layout reference name {0} of class {1}. GDS2 requires names be unique.".format(name,self.__class__),-1)

6
compiler/base/hierarchy_layout.py
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@ -447,6 +447,11 @@ class layout(lef.lef):
def gds_read(self): def gds_read(self):
"""Reads a GDSII file in the library and checks if it exists """Reads a GDSII file in the library and checks if it exists
Otherwise, start a new layout for dynamic generation.""" Otherwise, start a new layout for dynamic generation."""
# This must be done for netlist only mode too
if os.path.isfile(self.gds_file):
self.is_library_cell=True
if OPTS.netlist_only: if OPTS.netlist_only:
self.gds = None self.gds = None
return return
@ -454,7 +459,6 @@ class layout(lef.lef):
# open the gds file if it exists or else create a blank layout # open the gds file if it exists or else create a blank layout
if os.path.isfile(self.gds_file): if os.path.isfile(self.gds_file):
debug.info(3, "opening {}".format(self.gds_file)) debug.info(3, "opening {}".format(self.gds_file))
self.is_library_cell=True
self.gds = gdsMill.VlsiLayout(units=GDS["unit"]) self.gds = gdsMill.VlsiLayout(units=GDS["unit"])
reader = gdsMill.Gds2reader(self.gds) reader = gdsMill.Gds2reader(self.gds)
reader.loadFromFile(self.gds_file) reader.loadFromFile(self.gds_file)

20
compiler/base/pin_layout.py
View File

@ -62,6 +62,24 @@ class pin_layout:
else: else:
return False return False
def bbox(self, pin_list):
"""
Given a list of layout pins, create a bounding box layout.
"""
(ll, ur) = self.rect
min_x = ll.x
max_x = ur.x
min_y = ll.y
max_y = ur.y
for pin in pin_list:
min_x = min(min_x, pin.ll().x)
max_x = max(max_x, pin.ur().x)
min_y = min(min_y, pin.ll().y)
max_y = max(max_y, pin.ur().y)
self.rect = [vector(min_x,min_y),vector(max_x,max_y)]
def inflate(self, spacing=None): def inflate(self, spacing=None):
""" """
Inflate the rectangle by the spacing (or other rule) Inflate the rectangle by the spacing (or other rule)
@ -325,7 +343,7 @@ class pin_layout:
(r2_ll,r2_ur) = other.rect (r2_ll,r2_ur) = other.rect
def dist(x1, y1, x2, y2): def dist(x1, y1, x2, y2):
return sqrt((x2-x1)**2 + (y2-y1)**2) return math.sqrt((x2-x1)**2 + (y2-y1)**2)
left = r2_ur.x < r1_ll.x left = r2_ur.x < r1_ll.x
right = r1_ur.x < r2_ll.x right = r1_ur.x < r2_ll.x

3
compiler/gdsMill/gdsMill/vlsiLayout.py
View File

@ -148,13 +148,13 @@ class VlsiLayout:
structureNames=[] structureNames=[]
for name in self.structures: for name in self.structures:
structureNames.append(name) structureNames.append(name)
for name in self.structures: for name in self.structures:
if(len(self.structures[name].srefs)>0): #does this structure reference any others? if(len(self.structures[name].srefs)>0): #does this structure reference any others?
for sref in self.structures[name].srefs: #go through each reference for sref in self.structures[name].srefs: #go through each reference
if sref.sName in structureNames: #and compare to our list if sref.sName in structureNames: #and compare to our list
structureNames.remove(sref.sName) structureNames.remove(sref.sName)
debug.check(len(structureNames)==1,"Multiple possible root structures in the layout: {}".format(str(structureNames)))
self.rootStructureName = structureNames[0] self.rootStructureName = structureNames[0]
def traverseTheHierarchy(self, startingStructureName=None, delegateFunction = None, def traverseTheHierarchy(self, startingStructureName=None, delegateFunction = None,
@ -304,6 +304,7 @@ class VlsiLayout:
debug.info(1,"DEBUG: Structure %s Found"%StructureName) debug.info(1,"DEBUG: Structure %s Found"%StructureName)
StructureFound = True StructureFound = True
debug.check(StructureFound,"Could not find layout to instantiate {}".format(StructureName))
# If layoutToAdd is a unique object (not this), then copy hierarchy, # If layoutToAdd is a unique object (not this), then copy hierarchy,

113
compiler/modules/bank.py
View File

@ -61,11 +61,11 @@ class bank(design.design):
#self.add_lvs_correspondence_points() #self.add_lvs_correspondence_points()
# Remember the bank center for further placement # Remember the bank center for further placement
self.bank_center=self.offset_all_coordinates().scale(-1,-1) self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1)
self.bank_array_ur = self.bitcell_array_inst.ur()
self.DRC_LVS() self.DRC_LVS()
def add_pins(self): def add_pins(self):
""" Adding pins for Bank module""" """ Adding pins for Bank module"""
for port in self.read_ports: for port in self.read_ports:
@ -232,8 +232,8 @@ class bank(design.design):
self.row_decoder_offsets[port] = vector(-x_offset,0) self.row_decoder_offsets[port] = vector(-x_offset,0)
# LOWER LEFT QUADRANT # LOWER LEFT QUADRANT
# Place the col decoder right aligned with row decoder (x_offset doesn't change) # Place the col decoder left aligned with row decoder (x_offset doesn't change)
# Below the bitcell array # Below the bitcell array with well spacing
if self.col_addr_size > 0: if self.col_addr_size > 0:
y_offset = self.column_decoder.height y_offset = self.column_decoder.height
else: else:
@ -290,8 +290,11 @@ class bank(design.design):
# UPPER RIGHT QUADRANT # UPPER RIGHT QUADRANT
# Place the col decoder right aligned with row decoder (x_offset doesn't change) # Place the col decoder right aligned with row decoder (x_offset doesn't change)
# Below the bitcell array # Above the bitcell array with a well spacing
y_offset = self.bitcell_array.height + self.m2_gap if self.col_addr_size > 0:
y_offset = self.bitcell_array.height + self.column_decoder.height
else:
y_offset = self.bitcell_array.height
y_offset += 2*drc("well_to_well") y_offset += 2*drc("well_to_well")
self.column_decoder_offsets[port] = vector(x_offset,y_offset) self.column_decoder_offsets[port] = vector(x_offset,y_offset)
@ -723,7 +726,7 @@ class bank(design.design):
for port in self.all_ports: for port in self.all_ports:
if port%2 == 1: if port%2 == 1:
mirror = "MY" mirror = "XY"
else: else:
mirror = "R0" mirror = "R0"
self.column_decoder_inst[port].place(offset=offsets[port], mirror=mirror) self.column_decoder_inst[port].place(offset=offsets[port], mirror=mirror)
@ -873,9 +876,9 @@ class bank(design.design):
if self.col_addr_size==0: if self.col_addr_size==0:
return return
bottom_inst = self.column_mux_array_inst[port] inst1 = self.column_mux_array_inst[port]
top_inst = self.precharge_array_inst[port] inst2 = self.precharge_array_inst[port]
self.connect_bitlines(top_inst, bottom_inst, self.num_cols) self.connect_bitlines(inst1, inst2, self.num_cols)
def route_column_mux_to_bitcell_array(self, port): def route_column_mux_to_bitcell_array(self, port):
""" Routing of BL and BR between col mux bitcell array """ """ Routing of BL and BR between col mux bitcell array """
@ -884,47 +887,50 @@ class bank(design.design):
if self.col_addr_size==0: if self.col_addr_size==0:
return return
bottom_inst = self.column_mux_array_inst[port] inst2 = self.column_mux_array_inst[port]
top_inst = self.bitcell_array_inst inst1 = self.bitcell_array_inst
self.connect_bitlines(top_inst, bottom_inst, self.num_cols) inst1_bl_name = self.bl_names[port]+"_{}"
inst1_br_name = self.br_names[port]+"_{}"
self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols,
inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
def route_sense_amp_to_column_mux_or_precharge_array(self, port): def route_sense_amp_to_column_mux_or_precharge_array(self, port):
""" Routing of BL and BR between sense_amp and column mux or precharge array """ """ Routing of BL and BR between sense_amp and column mux or precharge array """
bottom_inst = self.sense_amp_array_inst[port] inst2 = self.sense_amp_array_inst[port]
if self.col_addr_size>0: if self.col_addr_size>0:
# Sense amp is connected to the col mux # Sense amp is connected to the col mux
top_inst = self.column_mux_array_inst[port] inst1 = self.column_mux_array_inst[port]
top_bl = "bl_out_{}" inst1_bl_name = "bl_out_{}"
top_br = "br_out_{}" inst1_br_name = "br_out_{}"
else: else:
# Sense amp is directly connected to the precharge array # Sense amp is directly connected to the precharge array
top_inst = self.precharge_array_inst[port] inst1 = self.precharge_array_inst[port]
top_bl = "bl_{}" inst1_bl_name = "bl_{}"
top_br = "br_{}" inst1_br_name = "br_{}"
self.connect_bitlines(inst1=top_inst, inst2=bottom_inst, num_bits=self.word_size, self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
inst1_bl_name=top_bl, inst1_br_name=top_br) inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
def route_write_driver_to_column_mux_or_precharge_array(self, port): def route_write_driver_to_column_mux_or_bitcell_array(self, port):
""" Routing of BL and BR between sense_amp and column mux or precharge array """ """ Routing of BL and BR between sense_amp and column mux or bitcell array """
bottom_inst = self.write_driver_array_inst[port] inst2 = self.write_driver_array_inst[port]
if self.col_addr_size>0: if self.col_addr_size>0:
# Sense amp is connected to the col mux # Write driver is connected to the col mux
top_inst = self.column_mux_array_inst[port] inst1 = self.column_mux_array_inst[port]
top_bl = "bl_out_{}" inst1_bl_name = "bl_out_{}"
top_br = "br_out_{}" inst1_br_name = "br_out_{}"
else: else:
# Sense amp is directly connected to the precharge array # Write driver is directly connected to the bitcell array
top_inst = self.precharge_array_inst[port] inst1 = self.bitcell_array_inst
top_bl = "bl_{}" inst1_bl_name = self.bl_names[port]+"_{}"
top_br = "br_{}" inst1_br_name = self.br_names[port]+"_{}"
self.connect_bitlines(inst1=top_inst, inst2=bottom_inst, num_bits=self.word_size, self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
inst1_bl_name=top_bl, inst1_br_name=top_br) inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
def route_write_driver_to_sense_amp(self, port): def route_write_driver_to_sense_amp(self, port):
""" Routing of BL and BR between write driver and sense amp """ """ Routing of BL and BR between write driver and sense amp """
@ -939,7 +945,7 @@ class bank(design.design):
for bit in range(self.word_size): for bit in range(self.word_size):
data_pin = self.sense_amp_array_inst[port].get_pin("data_{}".format(bit)) data_pin = self.sense_amp_array_inst[port].get_pin("data_{}".format(bit))
self.add_layout_pin_rect_center(text="dout{0}_{1}".format(self.read_ports[port],bit), self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port,bit),
layer=data_pin.layer, layer=data_pin.layer,
offset=data_pin.center(), offset=data_pin.center(),
height=data_pin.height(), height=data_pin.height(),
@ -965,6 +971,37 @@ class bank(design.design):
din_name = "din{0}_{1}".format(port,row) din_name = "din{0}_{1}".format(port,row)
self.copy_layout_pin(self.write_driver_array_inst[port], data_name, din_name) self.copy_layout_pin(self.write_driver_array_inst[port], data_name, din_name)
def channel_route_bitlines(self, inst1, inst2, num_bits,
inst1_bl_name="bl_{}", inst1_br_name="br_{}",
inst2_bl_name="bl_{}", inst2_br_name="br_{}"):
"""
Route the bl and br of two modules using the channel router.
"""
# determine top and bottom automatically.
# since they don't overlap, we can just check the bottom y coordinate.
if inst1.by() < inst2.by():
(bottom_inst, bottom_bl_name, bottom_br_name) = (inst1, inst1_bl_name, inst1_br_name)
(top_inst, top_bl_name, top_br_name) = (inst2, inst2_bl_name, inst2_br_name)
else:
(bottom_inst, bottom_bl_name, bottom_br_name) = (inst2, inst2_bl_name, inst2_br_name)
(top_inst, top_bl_name, top_br_name) = (inst1, inst1_bl_name, inst1_br_name)
# Channel route each mux separately since we don't minimize the number
# of tracks in teh channel router yet. If we did, we could route all the bits at once!
offset = bottom_inst.ul() + vector(0,self.m1_pitch)
for bit in range(num_bits):
bottom_names = [bottom_bl_name.format(bit), bottom_br_name.format(bit)]
top_names = [top_bl_name.format(bit), top_br_name.format(bit)]
route_map = list(zip(bottom_names, top_names))
bottom_pins = {key: bottom_inst.get_pin(key) for key in bottom_names }
top_pins = {key: top_inst.get_pin(key) for key in top_names }
all_pins = {**bottom_pins, **top_pins}
debug.check(len(all_pins)==len(bottom_pins)+len(top_pins),"Duplicate named pins in bitline channel route.")
self.create_horizontal_channel_route(route_map, all_pins, offset)
def connect_bitlines(self, inst1, inst2, num_bits, def connect_bitlines(self, inst1, inst2, num_bits,
inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst1_bl_name="bl_{}", inst1_br_name="br_{}",
inst2_bl_name="bl_{}", inst2_br_name="br_{}"): inst2_bl_name="bl_{}", inst2_br_name="br_{}"):
@ -1189,8 +1226,8 @@ class bank(design.design):
# clk to wordline_driver # clk to wordline_driver
control_signal = self.prefix+"clk_buf{}".format(port) control_signal = self.prefix+"clk_buf{}".format(port)
pin_pos = self.wordline_driver_inst[port].get_pin("en").uc() pin_pos = self.wordline_driver_inst[port].get_pin("en").bc()
mid_pos = pin_pos + vector(0,self.m1_pitch) mid_pos = pin_pos - vector(0,self.m1_pitch)
control_x_offset = self.bus_xoffset[port][control_signal].x control_x_offset = self.bus_xoffset[port][control_signal].x
control_pos = vector(control_x_offset, mid_pos.y) control_pos = vector(control_x_offset, mid_pos.y)
self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])

9
compiler/modules/bitcell_array.py
View File

@ -4,7 +4,7 @@ from tech import drc, spice
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
unique_id = 1
class bitcell_array(design.design): class bitcell_array(design.design):
""" """
@ -12,8 +12,13 @@ class bitcell_array(design.design):
and word line is connected by abutment. and word line is connected by abutment.
Connects the word lines and bit lines. Connects the word lines and bit lines.
""" """
unique_id = 1
def __init__(self, cols, rows, name="bitcell_array"): def __init__(self, cols, rows, name=""):
if name == "":
name = "bitcell_array_{0}x{1}_{2}".format(rows,cols,bitcell_array.unique_id)
bitcell_array.unique_id += 1
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))

12
compiler/modules/control_logic.py
View File

@ -45,7 +45,6 @@ class control_logic(design.design):
def create_layout(self): def create_layout(self):
""" Create layout and route between modules """ """ Create layout and route between modules """
self.route_rails()
self.place_instances() self.place_instances()
self.route_all() self.route_all()
@ -149,7 +148,7 @@ class control_logic(design.design):
def route_rails(self): def route_rails(self):
""" Add the input signal inverted tracks """ """ Add the input signal inverted tracks """
height = 4*self.inv1.height - self.m2_pitch height = self.control_logic_center.y - self.m2_pitch
offset = vector(self.ctrl_dff_array.width,0) offset = vector(self.ctrl_dff_array.width,0)
self.rail_offsets = self.create_vertical_bus("metal2", self.m2_pitch, offset, self.internal_bus_list, height) self.rail_offsets = self.create_vertical_bus("metal2", self.m2_pitch, offset, self.internal_bus_list, height)
@ -182,21 +181,21 @@ class control_logic(design.design):
row += 2 row += 2
if (self.port_type == "rw") or (self.port_type == "w"): if (self.port_type == "rw") or (self.port_type == "w"):
self.place_we_row(row=row) self.place_we_row(row=row)
pre_height = self.w_en_inst.uy() height = self.w_en_inst.uy()
control_center_y = self.w_en_inst.by() control_center_y = self.w_en_inst.uy()
row += 1 row += 1
if (self.port_type == "rw") or (self.port_type == "r"): if (self.port_type == "rw") or (self.port_type == "r"):
self.place_rbl_in_row(row=row) self.place_rbl_in_row(row=row)
self.place_sen_row(row=row+1) self.place_sen_row(row=row+1)
self.place_rbl(row=row+2) self.place_rbl(row=row+2)
pre_height = self.rbl_inst.uy() height = self.rbl_inst.uy()
control_center_y = self.rbl_inst.by() control_center_y = self.rbl_inst.by()
# This offset is used for placement of the control logic in the SRAM level. # This offset is used for placement of the control logic in the SRAM level.
self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y) self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y)
# Extra pitch on top and right # Extra pitch on top and right
self.height = pre_height + self.m3_pitch self.height = height + 2*self.m1_pitch
# Max of modules or logic rows # Max of modules or logic rows
if (self.port_type == "rw") or (self.port_type == "r"): if (self.port_type == "rw") or (self.port_type == "r"):
self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch
@ -205,6 +204,7 @@ class control_logic(design.design):
def route_all(self): def route_all(self):
""" Routing between modules """ """ Routing between modules """
self.route_rails()
self.route_dffs() self.route_dffs()
if (self.port_type == "rw") or (self.port_type == "w"): if (self.port_type == "rw") or (self.port_type == "w"):
self.route_wen() self.route_wen()

4
compiler/modules/dff_buf.py
View File

@ -12,11 +12,13 @@ class dff_buf(design.design):
with two inverters, of variable size, to provide q with two inverters, of variable size, to provide q
and qbar. This is to enable driving large fanout loads. and qbar. This is to enable driving large fanout loads.
""" """
unique_id = 1
def __init__(self, inv1_size=2, inv2_size=4, name=""): def __init__(self, inv1_size=2, inv2_size=4, name=""):
if name=="": if name=="":
name = "dff_buf_{0}_{1}".format(inv1_size, inv2_size) name = "dff_buf_{0}".format(dff_buf.unique_id)
dff_buf.unique_id += 1
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name)) debug.info(1, "Creating {}".format(self.name))

4
compiler/modules/dff_buf_array.py
View File

@ -11,13 +11,15 @@ class dff_buf_array(design.design):
This is a simple row (or multiple rows) of flops. This is a simple row (or multiple rows) of flops.
Unlike the data flops, these are never spaced out. Unlike the data flops, these are never spaced out.
""" """
unique_id = 1
def __init__(self, rows, columns, inv1_size=2, inv2_size=4, name=""): def __init__(self, rows, columns, inv1_size=2, inv2_size=4, name=""):
self.rows = rows self.rows = rows
self.columns = columns self.columns = columns
if name=="": if name=="":
name = "dff_buf_array_{0}x{1}".format(rows, columns) name = "dff_buf_array_{0}x{1}_{2}".format(rows, columns, dff_buf_array.unique_id)
dff_buf_array.unique_id += 1
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name)) debug.info(1, "Creating {}".format(self.name))
self.inv1_size = inv1_size self.inv1_size = inv1_size

4
compiler/modules/dff_inv.py
View File

@ -11,11 +11,13 @@ class dff_inv(design.design):
This is a simple DFF with an inverted output. Some DFFs This is a simple DFF with an inverted output. Some DFFs
do not have Qbar, so this will create it. do not have Qbar, so this will create it.
""" """
unique_id = 1
def __init__(self, inv_size=2, name=""): def __init__(self, inv_size=2, name=""):
if name=="": if name=="":
name = "dff_inv_{0}".format(inv_size) name = "dff_inv_{0}".format(dff_inv.unique_id)
dff_inv.unique_id += 1
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name)) debug.info(1, "Creating {}".format(self.name))
self.inv_size = inv_size self.inv_size = inv_size

4
compiler/modules/dff_inv_array.py
View File

@ -11,13 +11,15 @@ class dff_inv_array(design.design):
This is a simple row (or multiple rows) of flops. This is a simple row (or multiple rows) of flops.
Unlike the data flops, these are never spaced out. Unlike the data flops, these are never spaced out.
""" """
unique_id = 1
def __init__(self, rows, columns, inv_size=2, name=""): def __init__(self, rows, columns, inv_size=2, name=""):
self.rows = rows self.rows = rows
self.columns = columns self.columns = columns
if name=="": if name=="":
name = "dff_inv_array_{0}x{1}".format(rows, columns) name = "dff_inv_array_{0}x{1}_{2}".format(rows, columns, dff_inv_array.unique_id)
dff_inv_array.unique_id += 1
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name)) debug.info(1, "Creating {}".format(self.name))
self.inv_size = inv_size self.inv_size = inv_size

2
compiler/modules/hierarchical_predecode.py
View File

@ -267,7 +267,7 @@ class hierarchical_predecode(design.design):
# Find the x offsets for where the vias/pins should be placed # Find the x offsets for where the vias/pins should be placed
in_xoffset = self.in_inst[0].rx() in_xoffset = self.in_inst[0].rx()
out_xoffset = self.inv_inst[0].lx() out_xoffset = self.inv_inst[0].lx() - self.m1_space
for num in range(0,self.number_of_outputs): for num in range(0,self.number_of_outputs):
# this will result in duplicate polygons for rails, but who cares # this will result in duplicate polygons for rails, but who cares

2
compiler/modules/replica_bitline.py
View File

@ -90,7 +90,7 @@ class replica_bitline(design.design):
self.add_mod(self.bitcell) self.add_mod(self.bitcell)
# This is the replica bitline load column that is the height of our array # This is the replica bitline load column that is the height of our array
self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.bitcell_loads) self.rbl = bitcell_array(cols=1, rows=self.bitcell_loads)
self.add_mod(self.rbl) self.add_mod(self.rbl)
# FIXME: The FO and depth of this should be tuned # FIXME: The FO and depth of this should be tuned

14
compiler/router/grid_utils.py
View File

@ -3,6 +3,7 @@ Some utility functions for sets of grid cells.
""" """
import debug import debug
import math
from direction import direction from direction import direction
from vector3d import vector3d from vector3d import vector3d
@ -139,3 +140,16 @@ def flatten_set(curset):
else: else:
newset.update(flatten_set(c)) newset.update(flatten_set(c))
return newset return newset
def distance_set(coord, curset):
"""
Return the distance from a coordinate to any item in the set
"""
min_dist = math.inf
for c in curset:
min_dist = min(coord.euclidean_distance(c), min_dist)
return min_dist

31
compiler/router/pin_group.py
View File

@ -465,15 +465,22 @@ class pin_group:
if pin.contained_by_any(self.enclosures): if pin.contained_by_any(self.enclosures):
continue continue
# Find a connector in the cardinal directions
# If there is overlap, but it isn't contained, these could all be None
# These could also be none if the pin is diagonal from the enclosure
left_connector = self.find_left_connector(pin, self.enclosures) left_connector = self.find_left_connector(pin, self.enclosures)
right_connector = self.find_right_connector(pin, self.enclosures) right_connector = self.find_right_connector(pin, self.enclosures)
above_connector = self.find_above_connector(pin, self.enclosures) above_connector = self.find_above_connector(pin, self.enclosures)
below_connector = self.find_below_connector(pin, self.enclosures) below_connector = self.find_below_connector(pin, self.enclosures)
for connector in [left_connector, right_connector, above_connector, below_connector]: connector_list = [left_connector, right_connector, above_connector, below_connector]
if connector: filtered_list = list(filter(lambda x: x!=None, connector_list))
self.enclosures.append(connector) if (len(filtered_list)>0):
import copy
bbox_connector = copy.copy(pin)
bbox_connector.bbox(filtered_list)
self.enclosures.append(bbox_connector)
# Now, make sure each pin touches an enclosure. If not, add a connector. # Now, make sure each pin touches an enclosure. If not, add another (diagonal) connector.
# This could only happen when there was no enclosure in any cardinal direction from a pin # This could only happen when there was no enclosure in any cardinal direction from a pin
for pin_list in self.pins: for pin_list in self.pins:
if not self.overlap_any_shape(pin_list, self.enclosures): if not self.overlap_any_shape(pin_list, self.enclosures):
@ -495,6 +502,16 @@ class pin_group:
self.grids = pg1.grids | pg2.grids # OR the set of grid locations self.grids = pg1.grids | pg2.grids # OR the set of grid locations
self.secondary_grids = pg1.secondary_grids | pg2.secondary_grids self.secondary_grids = pg1.secondary_grids | pg2.secondary_grids
def add_group(self, pg):
"""
Combine the pin group into this one. This will add to the first item in the pins
so this should be used before there are disconnected pins.
"""
debug.check(len(self.pins)==1,"Don't know which group to add pins to.")
self.pins[0].update(*pg.pins) # Join the two lists of pins
self.grids |= pg.grids # OR the set of grid locations
self.secondary_grids |= pg.secondary_grids
def add_enclosure(self, cell): def add_enclosure(self, cell):
""" """
Add the enclosure shape to the given cell. Add the enclosure shape to the given cell.
@ -585,7 +602,7 @@ class pin_group:
# At least one of the groups must have some valid tracks # At least one of the groups must have some valid tracks
if (len(pin_set)==0 and len(blockage_set)==0): if (len(pin_set)==0 and len(blockage_set)==0):
debug.warning("Pin is very close to metal blockage.\nAttempting to expand blocked pin {}".format(self.pins)) #debug.warning("Pin is very close to metal blockage.\nAttempting to expand blocked pin {}".format(self.pins))
for pin_list in self.pins: for pin_list in self.pins:
for pin in pin_list: for pin in pin_list:
@ -639,7 +656,6 @@ class pin_group:
that is ensured to overlap the supply rail wire. that is ensured to overlap the supply rail wire.
It then adds rectangle(s) for the enclosure. It then adds rectangle(s) for the enclosure.
""" """
additional_set = set() additional_set = set()
# Check the layer of any element in the pin to determine which direction to route it # Check the layer of any element in the pin to determine which direction to route it
e = next(iter(start_set)) e = next(iter(start_set))
@ -663,3 +679,6 @@ class pin_group:
self.set_routed() self.set_routed()
self.enclosures = self.compute_enclosures() self.enclosures = self.compute_enclosures()

170
compiler/router/router.py
View File

@ -9,9 +9,10 @@ from pin_layout import pin_layout
from pin_group import pin_group from pin_group import pin_group
from vector import vector from vector import vector
from vector3d import vector3d from vector3d import vector3d
from globals import OPTS from globals import OPTS,print_time
from pprint import pformat from pprint import pformat
import grid_utils import grid_utils
from datetime import datetime
class router(router_tech): class router(router_tech):
""" """
@ -31,6 +32,7 @@ class router(router_tech):
# If didn't specify a gds blockage file, write it out to read the gds # If didn't specify a gds blockage file, write it out to read the gds
# This isn't efficient, but easy for now # This isn't efficient, but easy for now
#start_time = datetime.now()
if not gds_filename: if not gds_filename:
gds_filename = OPTS.openram_temp+"temp.gds" gds_filename = OPTS.openram_temp+"temp.gds"
self.cell.gds_write(gds_filename) self.cell.gds_write(gds_filename)
@ -40,6 +42,7 @@ class router(router_tech):
self.reader = gdsMill.Gds2reader(self.layout) self.reader = gdsMill.Gds2reader(self.layout)
self.reader.loadFromFile(gds_filename) self.reader.loadFromFile(gds_filename)
self.top_name = self.layout.rootStructureName self.top_name = self.layout.rootStructureName
#print_time("GDS read",datetime.now(), start_time)
### The pin data structures ### The pin data structures
# A map of pin names to a set of pin_layout structures # A map of pin names to a set of pin_layout structures
@ -127,8 +130,12 @@ class router(router_tech):
Pin can either be a label or a location,layer pair: [[x,y],layer]. Pin can either be a label or a location,layer pair: [[x,y],layer].
""" """
debug.info(1,"Finding pins for {}.".format(pin_name)) debug.info(1,"Finding pins for {}.".format(pin_name))
#start_time = datetime.now()
self.retrieve_pins(pin_name) self.retrieve_pins(pin_name)
#print_time("Retrieved pins",datetime.now(), start_time)
#start_time = datetime.now()
self.analyze_pins(pin_name) self.analyze_pins(pin_name)
#print_time("Analyzed pins",datetime.now(), start_time)
def find_blockages(self): def find_blockages(self):
""" """
@ -153,96 +160,97 @@ class router(router_tech):
# This will get all shapes as blockages and convert to grid units # This will get all shapes as blockages and convert to grid units
# This ignores shapes that were pins # This ignores shapes that were pins
#start_time = datetime.now()
self.find_blockages() self.find_blockages()
#print_time("Find blockags",datetime.now(), start_time)
# Convert the blockages to grid units # Convert the blockages to grid units
#start_time = datetime.now()
self.convert_blockages() self.convert_blockages()
#print_time("Find blockags",datetime.now(), start_time)
# This will convert the pins to grid units # This will convert the pins to grid units
# It must be done after blockages to ensure no DRCs between expanded pins and blocked grids # It must be done after blockages to ensure no DRCs between expanded pins and blocked grids
#start_time = datetime.now()
for pin in pin_list: for pin in pin_list:
self.convert_pins(pin) self.convert_pins(pin)
#print_time("Convert pins",datetime.now(), start_time)
#start_time = datetime.now()
for pin in pin_list: for pin in pin_list:
self.combine_adjacent_pins(pin) self.combine_adjacent_pins(pin)
#print_time("Combine pins",datetime.now(), start_time)
#self.write_debug_gds("debug_combine_pins.gds",stop_program=True) #self.write_debug_gds("debug_combine_pins.gds",stop_program=True)
# Separate any adjacent grids of differing net names to prevent wide metal DRC violations # Separate any adjacent grids of differing net names to prevent wide metal DRC violations
# Must be done before enclosing pins # Must be done before enclosing pins
#start_time = datetime.now()
self.separate_adjacent_pins(self.supply_rail_space_width) self.separate_adjacent_pins(self.supply_rail_space_width)
#print_time("Separate pins",datetime.now(), start_time)
# For debug # For debug
#self.separate_adjacent_pins(1) #self.separate_adjacent_pins(1)
# Enclose the continguous grid units in a metal rectangle to fix some DRCs # Enclose the continguous grid units in a metal rectangle to fix some DRCs
#start_time = datetime.now()
self.enclose_pins() self.enclose_pins()
#print_time("Enclose pins",datetime.now(), start_time)
#self.write_debug_gds("debug_enclose_pins.gds",stop_program=True) #self.write_debug_gds("debug_enclose_pins.gds",stop_program=True)
def combine_adjacent_pins_pass(self, pin_name): def combine_adjacent_pins(self, pin_name):
""" """
Find pins that have adjacent routing tracks and merge them into a Find pins that have adjacent routing tracks and merge them into a
single pin_group. The pins themselves may not be touching, but single pin_group. The pins themselves may not be touching, but
enclose_pis in the next step will ensure they are touching. enclose_pis in the next step will ensure they are touching.
""" """
debug.info(1,"Combining adjacent pins for {}.".format(pin_name))
# Make a copy since we are going to add to (and then reduce) this list # Find all adjacencies
pin_groups = self.pin_groups[pin_name].copy() adjacent_pins = {}
# Start as None to signal the first iteration
remove_indices = set()
for index1,pg1 in enumerate(self.pin_groups[pin_name]): for index1,pg1 in enumerate(self.pin_groups[pin_name]):
# Cannot combine more than once
if index1 in remove_indices:
continue
for index2,pg2 in enumerate(self.pin_groups[pin_name]): for index2,pg2 in enumerate(self.pin_groups[pin_name]):
# Cannot combine with yourself # Cannot combine with yourself, also don't repeat
if index1==index2: if index1<=index2:
continue continue
# Cannot combine more than once
if index2 in remove_indices:
continue
# Combine if at least 1 grid cell is adjacent # Combine if at least 1 grid cell is adjacent
if pg1.adjacent(pg2): if pg1.adjacent(pg2):
combined = pin_group(pin_name, [], self) if not index1 in adjacent_pins.keys():
combined.combine_groups(pg1, pg2) adjacent_pins[index1] = set([index2])
debug.info(3,"Combining {0} {1} {2}:".format(pin_name, index1, index2)) else:
debug.info(3, " {0}\n {1}".format(pg1.pins, pg2.pins)) adjacent_pins[index1].add(index2)
# Make a list of indices to ensure every group gets in the new set
all_indices = set([x for x in range(len(self.pin_groups[pin_name]))])
# Now reconstruct the new groups
new_pin_groups = []
for index1,index2_set in adjacent_pins.items():
# Remove the indices if they are added to the new set
all_indices.discard(index1)
all_indices.difference_update(index2_set)
# Create the combined group starting with the first item
combined = self.pin_groups[pin_name][index1]
# Add all of the other items that overlapped
for index2 in index2_set:
pg = self.pin_groups[pin_name][index2]
combined.add_group(pg)
debug.info(3,"Combining {0} {1}:".format(pin_name, index2))
debug.info(3, " {0}\n {1}".format(combined.pins, pg.pins))
debug.info(3," --> {0}\n {1}".format(combined.pins,combined.grids)) debug.info(3," --> {0}\n {1}".format(combined.pins,combined.grids))
remove_indices.update([index1,index2]) new_pin_groups.append(combined)
pin_groups.append(combined)
break
# Remove them in decreasing order to not invalidate the indices # Add the pin groups that weren't added to the new set
debug.info(4,"Removing {}".format(sorted(remove_indices))) for index in all_indices:
for i in sorted(remove_indices, reverse=True): new_pin_groups.append(self.pin_groups[pin_name][index])
del pin_groups[i]
old_size = len(self.pin_groups[pin_name])
# Use the new pin group! # Use the new pin group!
self.pin_groups[pin_name] = pin_groups self.pin_groups[pin_name] = new_pin_groups
removed_pairs = old_size - len(new_pin_groups)
removed_pairs = int(len(remove_indices)/2) debug.info(1, "Combined {0} pin groups for {1}".format(removed_pairs,pin_name))
debug.info(1, "Combined {0} pin pairs for {1}".format(removed_pairs,pin_name))
return removed_pairs return removed_pairs
def combine_adjacent_pins(self, pin_name):
"""
Make multiple passes of the combine adjacent pins until we have no
more combinations or hit an iteration limit.
"""
debug.info(1,"Combining adjacent pins for {}.".format(pin_name))
# Start as None to signal the first iteration
num_removed_pairs = None
# Just used in case there's a circular combination or something weird
for iteration_count in range(10):
num_removed_pairs = self.combine_adjacent_pins_pass(pin_name)
if num_removed_pairs==0:
break
else:
debug.warning("Did not converge combining adjacent pins in supply router.")
def separate_adjacent_pins(self, separation): def separate_adjacent_pins(self, separation):
""" """
@ -271,7 +279,7 @@ class router(router_tech):
debug.info(1,"Comparing {0} and {1} adjacency".format(pin_name1, pin_name2)) debug.info(1,"Comparing {0} and {1} adjacency".format(pin_name1, pin_name2))
for index1,pg1 in enumerate(self.pin_groups[pin_name1]): for index1,pg1 in enumerate(self.pin_groups[pin_name1]):
for index2,pg2 in enumerate(self.pin_groups[pin_name2]): for index2,pg2 in enumerate(self.pin_groups[pin_name2]):
# FIXME: Use separation distance and edge grids only # FIgXME: Use separation distance and edge grids only
grids_g1, grids_g2 = pg1.adjacent_grids(pg2, separation) grids_g1, grids_g2 = pg1.adjacent_grids(pg2, separation)
# These should have the same length, so... # These should have the same length, so...
if len(grids_g1)>0: if len(grids_g1)>0:
@ -507,7 +515,7 @@ class router(router_tech):
# scale the size bigger to include neaby tracks # scale the size bigger to include neaby tracks
ll=ll.scale(self.track_factor).floor() ll=ll.scale(self.track_factor).floor()
ur=ur.scale(self.track_factor).ceil() ur=ur.scale(self.track_factor).ceil()
#print(pin)
# Keep tabs on tracks with sufficient and insufficient overlap # Keep tabs on tracks with sufficient and insufficient overlap
sufficient_list = set() sufficient_list = set()
insufficient_list = set() insufficient_list = set()
@ -515,35 +523,50 @@ class router(router_tech):
zindex=self.get_zindex(pin.layer_num) zindex=self.get_zindex(pin.layer_num)
for x in range(int(ll[0])+expansion,int(ur[0])+1+expansion): for x in range(int(ll[0])+expansion,int(ur[0])+1+expansion):
for y in range(int(ll[1]+expansion),int(ur[1])+1+expansion): for y in range(int(ll[1]+expansion),int(ur[1])+1+expansion):
debug.info(4,"Converting [ {0} , {1} ]".format(x,y))
(full_overlap,partial_overlap) = self.convert_pin_coord_to_tracks(pin, vector3d(x,y,zindex)) (full_overlap,partial_overlap) = self.convert_pin_coord_to_tracks(pin, vector3d(x,y,zindex))
if full_overlap: if full_overlap:
sufficient_list.update([full_overlap]) sufficient_list.update([full_overlap])
if partial_overlap: if partial_overlap:
insufficient_list.update([partial_overlap]) insufficient_list.update([partial_overlap])
debug.info(4,"Converting [ {0} , {1} ] full={2} partial={3}".format(x,y, full_overlap, partial_overlap))
# Remove the blocked grids
sufficient_list.difference_update(self.blocked_grids)
insufficient_list.difference_update(self.blocked_grids)
if len(sufficient_list)>0: if len(sufficient_list)>0:
return sufficient_list return sufficient_list
elif expansion==0 and len(insufficient_list)>0: elif expansion==0 and len(insufficient_list)>0:
#Remove blockages and return the best to be patched best_pin = self.get_all_offgrid_pin(pin, insufficient_list)
insufficient_list.difference_update(self.blocked_grids) #print(best_pin)
return self.get_best_offgrid_pin(pin, insufficient_list) return best_pin
elif expansion>0: elif expansion>0:
#Remove blockages and return the nearest nearest_pin = self.get_furthest_offgrid_pin(pin, insufficient_list)
insufficient_list.difference_update(self.blocked_grids) return nearest_pin
return self.get_nearest_offgrid_pin(pin, insufficient_list)
else: else:
debug.error("Unable to find any overlapping grids.", -1) return set()
def get_all_offgrid_pin(self, pin, insufficient_list):
"""
Find a list of all pins with some overlap.
"""
#print("INSUFFICIENT LIST",insufficient_list)
# Find the coordinate with the most overlap
any_overlap = set()
for coord in insufficient_list:
full_pin = self.convert_track_to_pin(coord)
# Compute the overlap with that rectangle
overlap_rect=pin.compute_overlap(full_pin)
# Determine the max x or y overlap
max_overlap = max(overlap_rect)
if max_overlap>0:
any_overlap.update([coord])
return any_overlap
def get_best_offgrid_pin(self, pin, insufficient_list): def get_best_offgrid_pin(self, pin, insufficient_list):
""" """
Given a pin and a list of partial overlap grids: Find a list of the single pin with the most overlap.
1) Find the unblocked grids.
2) If one, use it.
3) If not, find the greatest overlap.
4) Add a pin with the most overlap to make it "on grid"
that is not blocked.
""" """
#print("INSUFFICIENT LIST",insufficient_list) #print("INSUFFICIENT LIST",insufficient_list)
# Find the coordinate with the most overlap # Find the coordinate with the most overlap
@ -561,6 +584,23 @@ class router(router_tech):
return set([best_coord]) return set([best_coord])
def get_furthest_offgrid_pin(self, pin, insufficient_list):
"""
Get a grid cell that is the furthest from the blocked grids.
"""
#print("INSUFFICIENT LIST",insufficient_list)
# Find the coordinate with the most overlap
best_coord = None
best_dist = math.inf
for coord in insufficient_list:
min_dist = grid_utils.distance_set(coord, self.blocked_grids)
if min_dist<best_dist:
best_dist=min_dist
best_coord=coord
return set([best_coord])
def get_nearest_offgrid_pin(self, pin, insufficient_list): def get_nearest_offgrid_pin(self, pin, insufficient_list):
""" """
Given a pin and a list of grid cells (probably non-overlapping), Given a pin and a list of grid cells (probably non-overlapping),

11
compiler/router/supply_router.py
View File

@ -2,13 +2,14 @@ import gdsMill
import tech import tech
import math import math
import debug import debug
from globals import OPTS from globals import OPTS,print_time
from contact import contact from contact import contact
from pin_group import pin_group from pin_group import pin_group
from pin_layout import pin_layout from pin_layout import pin_layout
from vector3d import vector3d from vector3d import vector3d
from router import router from router import router
from direction import direction from direction import direction
from datetime import datetime
import grid import grid
import grid_utils import grid_utils
@ -68,10 +69,13 @@ class supply_router(router):
self.compute_supply_rail_dimensions() self.compute_supply_rail_dimensions()
# Get the pin shapes # Get the pin shapes
#start_time = datetime.now()
self.find_pins_and_blockages([self.vdd_name, self.gnd_name]) self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
#print_time("Pins and blockages",datetime.now(), start_time)
#self.write_debug_gds("pin_enclosures.gds",stop_program=True) #self.write_debug_gds("pin_enclosures.gds",stop_program=True)
# Add the supply rails in a mesh network and connect H/V with vias # Add the supply rails in a mesh network and connect H/V with vias
#start_time = datetime.now()
# Block everything # Block everything
self.prepare_blockages(self.gnd_name) self.prepare_blockages(self.gnd_name)
# Determine the rail locations # Determine the rail locations
@ -82,15 +86,20 @@ class supply_router(router):
# Determine the rail locations # Determine the rail locations
self.route_supply_rails(self.vdd_name,1) self.route_supply_rails(self.vdd_name,1)
#self.write_debug_gds("debug_rails.gds",stop_program=True) #self.write_debug_gds("debug_rails.gds",stop_program=True)
#print_time("Supply rails",datetime.now(), start_time)
#start_time = datetime.now()
self.route_simple_overlaps(vdd_name) self.route_simple_overlaps(vdd_name)
self.route_simple_overlaps(gnd_name) self.route_simple_overlaps(gnd_name)
#print_time("Simple overlaps",datetime.now(), start_time)
#self.write_debug_gds("debug_simple_route.gds",stop_program=False) #self.write_debug_gds("debug_simple_route.gds",stop_program=False)
# Route the supply pins to the supply rails # Route the supply pins to the supply rails
# Route vdd first since we want it to be shorter # Route vdd first since we want it to be shorter
#start_time = datetime.now()
self.route_pins_to_rails(vdd_name) self.route_pins_to_rails(vdd_name)
self.route_pins_to_rails(gnd_name) self.route_pins_to_rails(gnd_name)
#print_time("Routing",datetime.now(), start_time)
#self.write_debug_gds("debug_pin_routes.gds",stop_program=True) #self.write_debug_gds("debug_pin_routes.gds",stop_program=True)
#self.write_debug_gds("final.gds",False) #self.write_debug_gds("final.gds",False)

6
compiler/router/vector3d.py
View File

@ -164,9 +164,13 @@ class vector3d():
return vector3d(min(self.x,other.x),min(self.y,other.y),min(self.z,other.z)) return vector3d(min(self.x,other.x),min(self.y,other.y),min(self.z,other.z))
def distance(self, other): def distance(self, other):
""" Return the planar distance between two values """ """ Return the manhattan distance between two values """
return abs(self.x-other.x)+abs(self.y-other.y) return abs(self.x-other.x)+abs(self.y-other.y)
def euclidean_distance(self, other):
""" Return the euclidean distance between two values """
return math.sqrt((self.x-other.x)**2+(self.y-other.y)**2)
def adjacent(self, other): def adjacent(self, other):
""" Is the one grid adjacent in any planar direction to the other """ """ Is the one grid adjacent in any planar direction to the other """

105
compiler/sram_1bank.py
View File

@ -43,10 +43,10 @@ class sram_1bank(sram_base):
self.data_dff_insts = self.create_data_dff() self.data_dff_insts = self.create_data_dff()
def place_modules(self): def place_instances(self):
""" """
This places the modules for a single bank SRAM with control This places the instances for a single bank SRAM with control
logic. logic and up to 2 ports.
""" """
# No orientation or offset # No orientation or offset
@ -57,38 +57,76 @@ class sram_1bank(sram_base):
# the sense amps/column mux and cell array) # the sense amps/column mux and cell array)
# The x-coordinate is placed to allow a single clock wire (plus an extra pitch) # The x-coordinate is placed to allow a single clock wire (plus an extra pitch)
# up to the row address DFFs. # up to the row address DFFs.
for port in self.all_ports: control_pos = [None]*len(self.all_ports)
control_pos = vector(-self.control_logic_rw.width - 2*self.m2_pitch, row_addr_pos = [None]*len(self.all_ports)
self.bank.bank_center.y - self.control_logic_rw.control_logic_center.y) col_addr_pos = [None]*len(self.all_ports)
self.control_logic_insts[port].place(control_pos) data_pos = [None]*len(self.all_ports)
# The row address bits are placed above the control logic aligned on the right.
row_addr_pos = vector(self.control_logic_insts[0].rx() - self.row_addr_dff.width,
self.control_logic_insts[0].uy())
self.row_addr_dff_insts[port].place(row_addr_pos)
# This is M2 pitch even though it is on M1 to help stem via spacings on the trunk # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
data_gap = -self.m2_pitch*(self.word_size+1) data_gap = self.m2_pitch*(self.word_size+1)
# Add the column address below the bank under the control # Port 0
# The column address flops are aligned with the data flops port = 0
# This includes 2 M2 pitches for the row addr clock line
control_pos[port] = vector(-self.control_logic_insts[port].width - 2*self.m2_pitch,
self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
self.control_logic_insts[port].place(control_pos[port])
# The row address bits are placed above the control logic aligned on the right.
x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width
# It is aove the control logic but below the top of the bitcell array
y_offset = max(self.control_logic_insts[port].uy(), self.bank.bank_array_ur.y - self.row_addr_dff_insts[port].height)
row_addr_pos[port] = vector(x_offset, y_offset)
self.row_addr_dff_insts[port].place(row_addr_pos[port])
# Add the col address flops below the bank to the left of the lower-left of bank array
if self.col_addr_dff: if self.col_addr_dff:
col_addr_pos = vector(self.bank.bank_center.x - self.col_addr_dff.width - self.bank.central_bus_width, col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.central_bus_width,
data_gap - self.col_addr_dff.height) -data_gap - self.col_addr_dff_insts[port].height)
self.col_addr_dff_insts[port].place(col_addr_pos) self.col_addr_dff_insts[port].place(col_addr_pos[port])
# Add the data flops below the bank to the right of the center of bank: # Add the data flops below the bank to the right of the lower-left of bank array
# This relies on the center point of the bank: # This relies on the lower-left of the array of the bank
# decoder in upper left, bank in upper right, sensing in lower right. # decoder in upper left, bank in upper right, sensing in lower right.
# These flops go below the sensing and leave a gap to channel route to the # These flops go below the sensing and leave a gap to channel route to the
# sense amps. # sense amps.
data_pos = vector(self.bank.bank_center.x, if port in self.write_ports:
data_gap - self.data_dff.height) data_pos[port] = vector(self.bank.bank_array_ll.x,
self.data_dff_insts[port].place(data_pos) -data_gap - self.data_dff_insts[port].height)
self.data_dff_insts[port].place(data_pos[port])
if len(self.all_ports)>1:
# Port 1
port = 1
# This includes 2 M2 pitches for the row addr clock line
control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2*self.m2_pitch,
self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
self.control_logic_insts[port].place(control_pos[port], mirror="MY")
# The row address bits are placed above the control logic aligned on the left.
x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width
# It is above the control logic but below the top of the bitcell array
y_offset = max(self.control_logic_insts[port].uy(), self.bank.bank_array_ur.y - self.row_addr_dff_insts[port].height)
row_addr_pos[port] = vector(x_offset, y_offset)
self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="MY")
# Add the col address flops above the bank to the right of the upper-right of bank array
if self.col_addr_dff:
col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.central_bus_width,
self.bank_inst.uy() + data_gap + self.col_addr_dff_insts[port].height)
self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX")
# Add the data flops above the bank to the left of the upper-right of bank array
# This relies on the upper-right of the array of the bank
# decoder in upper left, bank in upper right, sensing in lower right.
# These flops go below the sensing and leave a gap to channel route to the
# sense amps.
if port in self.write_ports:
data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
self.bank.uy() + data_gap + self.data_dff_insts[port].height)
self.data_dff_insts[port].place(data_pos[port], mirror="MX")
# two supply rails are already included in the bank, so just 2 here.
# self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
# self.height = self.bank.height
def add_layout_pins(self): def add_layout_pins(self):
""" """
@ -114,7 +152,7 @@ class sram_1bank(sram_base):
for bit in range(self.word_size): for bit in range(self.word_size):
self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "DIN{0}[{1}]".format(port,bit)) self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "DIN{0}[{1}]".format(port,bit))
def route(self): def route_layout(self):
""" Route a single bank SRAM """ """ Route a single bank SRAM """
self.add_layout_pins() self.add_layout_pins()
@ -152,16 +190,23 @@ class sram_1bank(sram_base):
mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y) mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y)
self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos]) self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos])
if port in self.write_ports:
data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk") data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
data_dff_clk_pos = data_dff_clk_pin.center() data_dff_clk_pos = data_dff_clk_pin.center()
mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y) mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y)
self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos]) self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos])
# This uses a metal2 track to the right of the control/row addr DFF # This uses a metal2 track to the right (for port0) of the control/row addr DFF
# to route vertically. # to route vertically. For port1, it is to the left.
control_clk_buf_pin = self.control_logic_insts[port].get_pin("clk_buf") control_clk_buf_pin = self.control_logic_insts[port].get_pin("clk_buf")
control_clk_buf_pos = control_clk_buf_pin.rc()
row_addr_clk_pin = self.row_addr_dff_insts[port].get_pin("clk") row_addr_clk_pin = self.row_addr_dff_insts[port].get_pin("clk")
if port%2:
control_clk_buf_pos = control_clk_buf_pin.lc()
row_addr_clk_pos = row_addr_clk_pin.lc()
mid1_pos = vector(self.row_addr_dff_insts[port].lx() - self.m2_pitch,
row_addr_clk_pos.y)
else:
control_clk_buf_pos = control_clk_buf_pin.rc()
row_addr_clk_pos = row_addr_clk_pin.rc() row_addr_clk_pos = row_addr_clk_pin.rc()
mid1_pos = vector(self.row_addr_dff_insts[port].rx() + self.m2_pitch, mid1_pos = vector(self.row_addr_dff_insts[port].rx() + self.m2_pitch,
row_addr_clk_pos.y) row_addr_clk_pos.y)

15
compiler/sram_base.py
View File

@ -75,8 +75,9 @@ class sram_base(design):
def create_layout(self): def create_layout(self):
""" Layout creation """ """ Layout creation """
self.place_modules() self.place_instances()
self.route()
self.route_layout()
self.add_lvs_correspondence_points() self.add_lvs_correspondence_points()
@ -225,12 +226,12 @@ class sram_base(design):
words_per_row=self.words_per_row, words_per_row=self.words_per_row,
port_type="rw") port_type="rw")
self.add_mod(self.control_logic_rw) self.add_mod(self.control_logic_rw)
if len(self.write_ports)>0: if len(self.writeonly_ports)>0:
self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row, words_per_row=self.words_per_row,
port_type="w") port_type="w")
self.add_mod(self.control_logic_w) self.add_mod(self.control_logic_w)
if len(self.read_ports)>0: if len(self.readonly_ports)>0:
self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row, words_per_row=self.words_per_row,
port_type="r") port_type="r")
@ -369,9 +370,13 @@ class sram_base(design):
def create_data_dff(self): def create_data_dff(self):
""" Add and place all data flops """ """ Add and place all data flops """
insts = [] insts = []
for port in self.write_ports: for port in self.all_ports:
if port in self.write_ports:
insts.append(self.add_inst(name="data_dff{}".format(port), insts.append(self.add_inst(name="data_dff{}".format(port),
mod=self.data_dff)) mod=self.data_dff))
else:
insts.append(None)
continue
# inputs, outputs/output/bar # inputs, outputs/output/bar
inputs = [] inputs = []

60
compiler/tests/14_replica_bitline_multiport_test.py Executable file
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@ -0,0 +1,60 @@
#!/usr/bin/env python3
"""
Run a test on a multiport replica bitline
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class replica_bitline_multiport_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import replica_bitline
stages=4
fanout=4
rows=13
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
# check replica bitline in pbitcell multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

57
compiler/tests/14_replica_bitline_test.py
View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
""" """
Run a test on a delay chain Run a test on a replica bitline
""" """
import unittest import unittest
@ -32,61 +32,6 @@ class replica_bitline_test(openram_test):
a = replica_bitline.replica_bitline(stages,fanout,rows) a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a) self.local_check(a)
#check replica bitline in handmade multi-port 1rw+1r cell
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
stages=4
fanout=4
rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
stages=8
rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
# check replica bitline in pbitcell multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
stages=4
fanout=4
rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
stages=8
rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
stages=4
fanout=4
rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
stages=8
rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
globals.end_openram() globals.end_openram()

44
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py Executable file
View File

@ -0,0 +1,44 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class psram_1bank_2mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.num_words=32
c.words_per_row=2
debug.info(1, "Single bank two way column mux 1w/1r with control logic")
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

43
compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py Executable file
View File

@ -0,0 +1,43 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank, 2 port SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class sram_1bank_2mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.words_per_row=2
debug.info(1, "Single bank, two way column mux 1rw, 1r with control logic")
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

43
compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py Executable file
View File

@ -0,0 +1,43 @@
#!/usr/bin/env python3
"""
Run a regression test on a 1 bank, 2 port SRAM
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class sram_1bank_nomux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
c = sram_config(word_size=4,
num_words=16,
num_banks=1)
c.words_per_row=1
debug.info(1, "Single bank, no column mux 1rw, 1r with control logic")
a = sram(c, "sram")
self.local_check(a, final_verification=True)
globals.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

BIN
docs/figs/sense_amp_schem.pdf
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