mirror of https://github.com/VLSIDA/OpenRAM.git
check for cell prop names list
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825375d76d
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@ -26,10 +26,16 @@ class design(hierarchy_design):
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# This allows us to use different GDS/spice circuits for hard cells instead of the default ones
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# This allows us to use different GDS/spice circuits for hard cells instead of the default ones
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# Except bitcell names are generated automatically by the globals.py setup_bitcells routines
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# Except bitcell names are generated automatically by the globals.py setup_bitcells routines
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# depending on the number of ports.
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# depending on the number of ports.
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if name in props.names:
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if name in props.names:
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cell_name = props.names[name]
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if isinstance(name , list):
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num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
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cell_name = props.names[name][num_ports]
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else:
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cell_name = props.name[name]
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elif not cell_name:
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elif not cell_name:
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cell_name = name
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cell_name = nacell_name = props.name[name]
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super().__init__(name, cell_name)
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super().__init__(name, cell_name)
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# This means it is a custom cell.
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# This means it is a custom cell.
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