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Fixing power via problems in freepdk45

This commit is contained in:
Matt Guthaus 2018-07-19 10:23:08 -07:00
parent 9983408fa3
commit 51958814a0
2 changed files with 19 additions and 13 deletions
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3
compiler/base/hierarchy_layout.py
View File

@ -662,7 +662,8 @@ class layout(lef.lef):
offset=loc, offset=loc,
rotate=90) rotate=90)
self.add_via_center(layers=("metal2", "via2", "metal3"), self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=loc) offset=loc,
rotate=90)
self.add_layout_pin_rect_center(text=name, self.add_layout_pin_rect_center(text=name,
layer="metal3", layer="metal3",
offset=loc) offset=loc)

29
compiler/modules/delay_chain.py
View File

@ -35,6 +35,7 @@ class delay_chain(design.design):
self.add_pins() self.add_pins()
self.create_module() self.create_module()
self.add_inverters()
self.route_inverters() self.route_inverters()
self.add_layout_pins() self.add_layout_pins()
self.DRC_LVS() self.DRC_LVS()
@ -58,8 +59,6 @@ class delay_chain(design.design):
self.height = len(self.fanout_list)*self.inv.height self.height = len(self.fanout_list)*self.inv.height
self.width = (max(self.fanout_list)+1) * self.inv.width self.width = (max(self.fanout_list)+1) * self.inv.width
self.add_inverters()
def add_inverters(self): def add_inverters(self):
""" Add the inverters and connect them based on the stage list """ """ Add the inverters and connect them based on the stage list """
@ -164,17 +163,23 @@ class delay_chain(design.design):
""" Add vdd and gnd rails and the input/output. Connect the gnd rails internally on """ Add vdd and gnd rails and the input/output. Connect the gnd rails internally on
the top end with no input/output to obstruct. """ the top end with no input/output to obstruct. """
# Add power and ground to all the cells except:
# the fanout driver, the right-most load
# The routing to connect the loads is over the first and last cells
for pin_name in ["vdd", "gnd"]: for pin_name in ["vdd", "gnd"]:
for driver in self.driver_inst_list: # We have an even number of drivers and must only do every other
pin = driver.get_pin(pin_name) # supply rail
start = pin.lc() for i in range(len(self.driver_inst_list),2):
end = start + vector(self.width,0) inv = self.driver_inst_list[i]
self.add_power_pin(pin_name, start) for load in self.load_inst_map[inv]:
self.add_power_pin(pin_name, end) if load in self.rightest_load_inst:
self.add_rect(layer="metal1", continue
offset=pin.ll(), pin = load.get_pin(pin_name)
width=self.width, self.add_power_pin(pin_name, pin.center())
height=pin.height()) # self.add_rect(layer="metal1",
# offset=pin.ll(),
# width=self.width,
# height=pin.height())
# input is A pin of first inverter # input is A pin of first inverter
a_pin = self.driver_inst_list[0].get_pin("A") a_pin = self.driver_inst_list[0].get_pin("A")