luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Convert pgates to use ptx through the factory

This commit is contained in:
Matt Guthaus 2019-01-16 16:30:31 -08:00
parent a418431a42
commit 5192a01f2d
7 changed files with 60 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
compiler/pgates/pgate.py
View File

@ -2,7 +2,6 @@ import contact
import design import design
import debug import debug
from tech import drc, parameter, spice from tech import drc, parameter, spice
from ptx import ptx
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
@ -24,7 +23,7 @@ class pgate(design.design):
def connect_pin_to_rail(self,inst,pin,supply): def connect_pin_to_rail(self,inst,pin,supply):
""" Conencts a ptx pin to a supply rail. """ """ Connects a ptx pin to a supply rail. """
source_pin = inst.get_pin(pin) source_pin = inst.get_pin(pin)
supply_pin = self.get_pin(supply) supply_pin = self.get_pin(supply)
if supply_pin.overlaps(source_pin): if supply_pin.overlaps(source_pin):

28
compiler/pgates/pinv.py
View File

@ -2,12 +2,12 @@ import contact
import pgate import pgate
import debug import debug
from tech import drc, parameter, spice from tech import drc, parameter, spice
from ptx import ptx
from vector import vector from vector import vector
from math import ceil from math import ceil
from globals import OPTS from globals import OPTS
from utils import round_to_grid from utils import round_to_grid
import logical_effort import logical_effort
from sram_factory import factory
class pinv(pgate.pgate): class pinv(pgate.pgate):
""" """
@ -82,8 +82,8 @@ class pinv(pgate.pgate):
# Sanity check. can we make an inverter in the height with minimum tx sizes? # Sanity check. can we make an inverter in the height with minimum tx sizes?
# Assume we need 3 metal 1 pitches (2 power rails, one between the tx for the drain) # Assume we need 3 metal 1 pitches (2 power rails, one between the tx for the drain)
# plus the tx height # plus the tx height
nmos = ptx(tx_type="nmos") nmos = factory.create(module_type="ptx", tx_type="nmos")
pmos = ptx(width=drc("minwidth_tx"), tx_type="pmos") pmos = factory.create(module_type="ptx", width=drc("minwidth_tx"), tx_type="pmos")
tx_height = nmos.poly_height + pmos.poly_height tx_height = nmos.poly_height + pmos.poly_height
# rotated m1 pitch or poly to active spacing # rotated m1 pitch or poly to active spacing
min_channel = max(contact.poly.width + self.m1_space, min_channel = max(contact.poly.width + self.m1_space,
@ -143,18 +143,20 @@ class pinv(pgate.pgate):
def add_ptx(self): def add_ptx(self):
""" Create the PMOS and NMOS transistors. """ """ Create the PMOS and NMOS transistors. """
self.nmos = ptx(width=self.nmos_width, self.nmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.nmos_width,
tx_type="nmos", mults=self.tx_mults,
connect_poly=True, tx_type="nmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.nmos) self.add_mod(self.nmos)
self.pmos = ptx(width=self.pmos_width, self.pmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.pmos_width,
tx_type="pmos", mults=self.tx_mults,
connect_poly=True, tx_type="pmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.pmos) self.add_mod(self.pmos)
def route_supply_rails(self): def route_supply_rails(self):

24
compiler/pgates/pnand2.py
View File

@ -2,10 +2,10 @@ import contact
import pgate import pgate
import debug import debug
from tech import drc, parameter, spice from tech import drc, parameter, spice
from ptx import ptx
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
import logical_effort import logical_effort
from sram_factory import factory
class pnand2(pgate.pgate): class pnand2(pgate.pgate):
""" """
@ -56,18 +56,20 @@ class pnand2(pgate.pgate):
def add_ptx(self): def add_ptx(self):
""" Create the PMOS and NMOS transistors. """ """ Create the PMOS and NMOS transistors. """
self.nmos = ptx(width=self.nmos_width, self.nmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.nmos_width,
tx_type="nmos", mults=self.tx_mults,
connect_poly=True, tx_type="nmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.nmos) self.add_mod(self.nmos)
self.pmos = ptx(width=self.pmos_width, self.pmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.pmos_width,
tx_type="pmos", mults=self.tx_mults,
connect_poly=True, tx_type="pmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.pmos) self.add_mod(self.pmos)
def setup_layout_constants(self): def setup_layout_constants(self):

26
compiler/pgates/pnand3.py
View File

@ -2,9 +2,9 @@ import contact
import pgate import pgate
import debug import debug
from tech import drc, parameter, spice from tech import drc, parameter, spice
from ptx import ptx
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from sram_factory import factory
class pnand3(pgate.pgate): class pnand3(pgate.pgate):
""" """
@ -56,18 +56,20 @@ class pnand3(pgate.pgate):
def add_ptx(self): def add_ptx(self):
""" Create the PMOS and NMOS transistors. """ """ Create the PMOS and NMOS transistors. """
self.nmos = ptx(width=self.nmos_width, self.nmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.nmos_width,
tx_type="nmos", mults=self.tx_mults,
connect_poly=True, tx_type="nmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.nmos) self.add_mod(self.nmos)
self.pmos = ptx(width=self.pmos_width, self.pmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.pmos_width,
tx_type="pmos", mults=self.tx_mults,
connect_poly=True, tx_type="pmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.pmos) self.add_mod(self.pmos)
def setup_layout_constants(self): def setup_layout_constants(self):
@ -88,7 +90,7 @@ class pnand3(pgate.pgate):
self.output_pos = vector(0,0.5*self.height) self.output_pos = vector(0,0.5*self.height)
# This is the extra space needed to ensure DRC rules to the active contacts # This is the extra space needed to ensure DRC rules to the active contacts
nmos = ptx(tx_type="nmos") nmos = factory.create(module_type="ptx", tx_type="nmos")
extra_contact_space = max(-nmos.get_pin("D").by(),0) extra_contact_space = max(-nmos.get_pin("D").by(),0)
# This is a poly-to-poly of a flipped cell # This is a poly-to-poly of a flipped cell
self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space, self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space,

24
compiler/pgates/pnor2.py
View File

@ -2,9 +2,9 @@ import contact
import pgate import pgate
import debug import debug
from tech import drc, parameter, spice from tech import drc, parameter, spice
from ptx import ptx
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from sram_factory import factory
class pnor2(pgate.pgate): class pnor2(pgate.pgate):
""" """
@ -53,18 +53,20 @@ class pnor2(pgate.pgate):
def create_ptx(self): def create_ptx(self):
""" Create the PMOS and NMOS transistors. """ """ Create the PMOS and NMOS transistors. """
self.nmos = ptx(width=self.nmos_width, self.nmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.nmos_width,
tx_type="nmos", mults=self.tx_mults,
connect_poly=True, tx_type="nmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.nmos) self.add_mod(self.nmos)
self.pmos = ptx(width=self.pmos_width, self.pmos = factory.create(module_type="ptx",
mults=self.tx_mults, width=self.pmos_width,
tx_type="pmos", mults=self.tx_mults,
connect_poly=True, tx_type="pmos",
connect_active=True) connect_poly=True,
connect_active=True)
self.add_mod(self.pmos) self.add_mod(self.pmos)
def setup_layout_constants(self): def setup_layout_constants(self):

6
compiler/pgates/precharge.py
View File

@ -2,7 +2,6 @@ import contact
import pgate import pgate
import debug import debug
from tech import drc, parameter from tech import drc, parameter
from ptx import ptx
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
@ -50,8 +49,9 @@ class precharge(pgate.pgate):
""" """
Initializes the upper and lower pmos Initializes the upper and lower pmos
""" """
self.pmos = ptx(width=self.ptx_width, self.pmos = factory.create(module_type="ptx",
tx_type="pmos") width=self.ptx_width,
tx_type="pmos")
self.add_mod(self.pmos) self.add_mod(self.pmos)

3
compiler/pgates/single_level_column_mux.py
View File

@ -3,7 +3,6 @@ import debug
from tech import drc from tech import drc
from vector import vector from vector import vector
import contact import contact
from ptx import ptx
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
@ -48,7 +47,7 @@ class single_level_column_mux(design.design):
# Adds nmos_lower,nmos_upper to the module # Adds nmos_lower,nmos_upper to the module
self.ptx_width = self.tx_size*drc("minwidth_tx") self.ptx_width = self.tx_size*drc("minwidth_tx")
self.nmos = ptx(width=self.ptx_width) self.nmos = factory.create(module_type="ptx", width=self.ptx_width)
self.add_mod(self.nmos) self.add_mod(self.nmos)