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dual port rba lvs clean again with cell library changes

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This commit is contained in:
Jesse Cirimelli-Low
2026-04-14 14:48:26 -07:00
parent b6d98c44d5
commit 515591a422
12 changed files with 116 additions and 62 deletions
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compiler/modules/capped_replica_bitcell_array.py
+1 -1
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@@ -20,7 +20,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
sides of a bitcell array.
"""
def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
super().__init__(name, rows, cols, column_offset=0)
super().__init__(name, rows, cols, column_offset=0, row_offset=0)
debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
rows,
cols,