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Jesse Cirimelli-Low
2026-04-28 14:04:42 -07:00
parent c7f3ac33cd
commit 5077282180
1 changed files with 1 additions and 1 deletions
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compiler/modules/bitcell_base_array.py
+1 -1
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@@ -151,7 +151,7 @@ class bitcell_base_array(design):
wl_names = self.cell.get_all_wl_names() wl_names = self.cell.get_all_wl_names()
for row in range(self.row_size): for row in range(self.row_size):
for port in self.all_ports: for port in self.all_ports:
wl_pin = self.cell_inst[self.row_size - 1 - row, 0].get_pin(wl_names[port]) wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
self.add_layout_pin(text="wl_{0}_{1}".format(port, row), self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
layer=wl_pin.layer, layer=wl_pin.layer,
offset=wl_pin.ll().scale(0, 1), offset=wl_pin.ll().scale(0, 1),