Fix up to SRAM level with new replica bitcell array ports.

2026-09-03 16:31:08 +02:00 · 2020-08-13 14:29:10 -07:00
parent a55909930f
commit 50525e70f4
3 changed files with 90 additions and 37 deletions
@@ -346,6 +346,7 @@ class sram_base(design, verilog, lef):
                temp.append("dout{0}[{1}]".format(port, bit))
        for port in self.all_ports:
            temp.append("rbl_bl{0}".format(port))
+            temp.append("rbl_br{0}".format(port))
        for port in self.write_ports:
            for bit in range(self.word_size + self.num_spare_cols):
                temp.append("bank_din{0}[{1}]".format(port, bit))