mirror of https://github.com/VLSIDA/OpenRAM.git
Merge 21868f9de7 into c99b134deb
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commit
4f976bb9bd
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@ -367,8 +367,8 @@ class lib:
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self.lib.write(" type (data){\n")
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.sram.word_size))
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self.lib.write(" bit_from : {0};\n".format(self.sram.word_size - 1))
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self.lib.write(" bit_width : {0};\n".format(self.sram.word_size + self.sram.num_spare_cols))
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self.lib.write(" bit_from : {0};\n".format(self.sram.word_size + self.sram.num_spare_cols - 1))
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self.lib.write(" bit_to : 0;\n")
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self.lib.write(" }\n\n")
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@ -432,7 +432,7 @@ class lib:
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self.lib.write(" }\n")
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self.lib.write(" pin(dout{0}[{1}:0]){{\n".format(read_port,self.sram.word_size-1))
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self.lib.write(" pin(dout{0}[{1}:0]){{\n".format(read_port,self.sram.word_size + self.sram.num_spare_cols - 1))
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_sense : non_unate; \n")
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self.lib.write(" related_pin : \"clk{0}\"; \n".format(read_port))
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@ -465,7 +465,7 @@ class lib:
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self.lib.write(" address : addr{0}; \n".format(write_port))
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self.lib.write(" clocked_on : clk{0}; \n".format(write_port))
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self.lib.write(" }\n")
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self.lib.write(" pin(din{0}[{1}:0]){{\n".format(write_port,self.sram.word_size-1))
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self.lib.write(" pin(din{0}[{1}:0]){{\n".format(write_port,self.sram.word_size + self.sram.num_spare_cols - 1))
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self.write_FF_setuphold(write_port)
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self.lib.write(" }\n") # pin
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self.lib.write(" }\n") #bus
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@ -513,6 +513,12 @@ class lib:
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ctrl_pin_names = ["csb{0}".format(port)]
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if port in self.readwrite_ports:
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ctrl_pin_names.append("web{0}".format(port))
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if port in self.write_ports:
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if self.sram.num_spare_cols == 1:
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ctrl_pin_names.append("spare_wen{0}".format(port))
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else:
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for bit in range(self.sram.num_spare_cols):
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ctrl_pin_names.append("spare_wen{0}[{1}]".format(port, bit))
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for i in ctrl_pin_names:
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self.lib.write(" pin({0})".format(i))
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