mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Merged and fixed conflicts with dev
This commit is contained in:
Hunter Nichols
@@ -1,9 +1,9 @@
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# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
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#
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import os
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import debug
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@@ -0,0 +1,248 @@
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# See LICENSE for licensing information.
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||||
#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
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||||
# All rights reserved.
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#
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import sys,re,shutil
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import debug
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import tech
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import math
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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from .delay import delay
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class bitline_delay(delay):
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"""Functions to test for the worst case delay in a target SRAM
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The current worst case determines a feasible period for the SRAM then tests
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several bits and record the delay and differences between the bits.
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"""
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def __init__(self, sram, spfile, corner):
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delay.__init__(self,sram,spfile,corner)
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self.period = tech.spice["feasible_period"]
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self.is_bitline_measure = True
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def create_signal_names(self):
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delay.create_signal_names(self)
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self.bl_signal_names = ["Xsram.Xbank0.bl", "Xsram.Xbank0.br"]
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self.sen_name = "Xsram.s_en"
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def create_measurement_names(self):
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"""Create measurement names. The names themselves currently define the type of measurement"""
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#Altering the names will crash the characterizer. TODO: object orientated approach to the measurements.
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self.bl_volt_meas_names = ["volt_bl", "volt_br"]
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self.bl_delay_meas_names = ["delay_bl", "delay_br"] #only used in SPICE simulation
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self.bl_delay_result_name = "delay_bl_vth" #Used in the return value
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def set_probe(self,probe_address, probe_data):
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""" Probe address and data can be set separately to utilize other
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functions in this characterizer besides analyze."""
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delay.set_probe(self,probe_address, probe_data)
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self.bitline_column = self.get_data_bit_column_number(probe_address, probe_data)
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def write_delay_measures(self):
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"""
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Write the measure statements to quantify the bitline voltage at sense amp enable 50%.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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for read_port in self.targ_read_ports:
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self.write_bitline_voltage_measures(read_port)
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self.write_bitline_delay_measures(read_port)
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def write_bitline_voltage_measures(self, port):
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"""
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Add measurments to capture the bitline voltages at 50% Sense amp enable
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"""
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debug.info(2, "Measuring bitline column={}, port={}".format(self.bitline_column,port))
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if len(self.all_ports) == 1: #special naming case for single port sram bitlines
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bitline_port = ""
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else:
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bitline_port = str(port)
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sen_port_name = "{}{}".format(self.sen_name,port)
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for (measure_name, bl_signal_name) in zip(self.bl_volt_meas_names, self.bl_signal_names):
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bl_port_name = "{}{}_{}".format(bl_signal_name, bitline_port, self.bitline_column)
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measure_port_name = "{}{}".format(measure_name,port)
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self.stim.gen_meas_find_voltage(measure_port_name, sen_port_name, bl_port_name, .5, "RISE", self.cycle_times[self.measure_cycles[port]["read0"]])
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def write_bitline_delay_measures(self, port):
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"""
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Write the measure statements to quantify the delay and power results for a read port.
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"""
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# add measure statements for delays/slews
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for (measure_name, bl_signal_name) in zip(self.bl_delay_meas_names, self.bl_signal_names):
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meas_values = self.get_delay_meas_values(measure_name, bl_signal_name, port)
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self.stim.gen_meas_delay(*meas_values)
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def get_delay_meas_values(self, delay_name, bitline_name, port):
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"""Get the values needed to generate a Spice measurement statement based on the name of the measurement."""
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if len(self.all_ports) == 1: #special naming case for single port sram bitlines
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bitline_port = ""
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else:
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bitline_port = str(port)
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meas_name="{0}{1}".format(delay_name, port)
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targ_name = "{0}{1}_{2}".format(bitline_name,bitline_port,self.bitline_column)
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half_vdd = 0.5 * self.vdd_voltage
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trig_val = half_vdd
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targ_val = self.vdd_voltage-tech.spice["v_threshold_typical"]
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trig_name = "clk{0}".format(port)
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trig_dir="FALL"
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targ_dir="FALL"
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#Half period added to delay measurement to negative clock edge
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trig_td = targ_td = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period/2
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return (meas_name,trig_name,targ_name,trig_val,targ_val,trig_dir,targ_dir,trig_td,targ_td)
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def gen_test_cycles_one_port(self, read_port, write_port):
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"""Sets a list of key time-points [ns] of the waveform (each rising edge)
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of the cycles to do a timing evaluation of a single port """
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# Create the inverse address for a scratch address
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inverse_address = self.calculate_inverse_address()
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# For now, ignore data patterns and write ones or zeros
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data_ones = "1"*self.word_size
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data_zeros = "0"*self.word_size
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if self.t_current == 0:
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self.add_noop_all_ports("Idle cycle (no positive clock edge)",
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inverse_address, data_zeros)
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self.add_write("W data 1 address {}".format(inverse_address),
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inverse_address,data_ones,write_port)
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self.add_write("W data 0 address {} to write value".format(self.probe_address),
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self.probe_address,data_zeros,write_port)
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self.measure_cycles[write_port]["write0"] = len(self.cycle_times)-1
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# This also ensures we will have a H->L transition on the next read
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self.add_read("R data 1 address {} to set DOUT caps".format(inverse_address),
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inverse_address,data_zeros,read_port)
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self.measure_cycles[read_port]["read1"] = len(self.cycle_times)-1
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self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address),
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self.probe_address,data_zeros,read_port)
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self.measure_cycles[read_port]["read0"] = len(self.cycle_times)-1
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def get_data_bit_column_number(self, probe_address, probe_data):
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"""Calculates bitline column number of data bit under test using bit position and mux size"""
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if self.sram.col_addr_size>0:
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col_address = int(probe_address[0:self.sram.col_addr_size],2)
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else:
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col_address = 0
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bl_column = int(self.sram.words_per_row*probe_data + col_address)
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return bl_column
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def run_delay_simulation(self):
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"""
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This tries to simulate a period and checks if the result works. If
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so, it returns True and the delays, slews, and powers. It
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works on the trimmed netlist by default, so powers do not
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include leakage of all cells.
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"""
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#Sanity Check
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debug.check(self.period > 0, "Target simulation period non-positive")
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result = [{} for i in self.all_ports]
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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self.stim.run_sim() #running sim prodoces spice output file.
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for port in self.targ_read_ports:
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#Parse and check the voltage measurements
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bl_volt_meas_dict = {}
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for mname in self.bl_volt_meas_names:
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mname_port = "{}{}".format(mname,port)
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volt_meas_val = parse_spice_list("timing", mname_port)
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if type(volt_meas_val)!=float:
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debug.error("Failed to Parse Bitline Voltage:\n\t\t{0}={1}".format(mname,volt_meas_val),1)
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bl_volt_meas_dict[mname] = volt_meas_val
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result[port].update(bl_volt_meas_dict)
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#Parse and check the delay measurements. Intended that one measurement will fail, save the delay that did not fail.
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bl_delay_meas_dict = {}
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values_added = 0 #For error checking
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for mname in self.bl_delay_meas_names: #Parse
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mname_port = "{}{}".format(mname,port)
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delay_meas_val = parse_spice_list("timing", mname_port)
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if type(delay_meas_val)==float: #Only add if value is float, do not error.
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bl_delay_meas_dict[self.bl_delay_result_name] = delay_meas_val * 1e9 #convert to ns
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values_added+=1
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debug.check(values_added>0, "Bitline delay measurements failed in SPICE simulation.")
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debug.check(values_added<2, "Both bitlines experienced a Vth drop, check simulation results.")
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result[port].update(bl_delay_meas_dict)
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# The delay is from the negative edge for our SRAM
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return (True,result)
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def check_bitline_all_results(self, results):
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"""Checks the bitline values measured for each tested port"""
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for port in self.targ_read_ports:
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self.check_bitline_port_results(results[port])
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def check_bitline_port_results(self, port_results):
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"""Performs three different checks for the bitline values: functionality, bitline swing from vdd, and differential bit swing"""
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bl_volt, br_volt = port_results["volt_bl"], port_results["volt_br"]
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self.check_functionality(bl_volt,br_volt)
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self.check_swing_from_vdd(bl_volt,br_volt)
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self.check_differential_swing(bl_volt,br_volt)
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def check_functionality(self, bl_volt, br_volt):
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"""Checks whether the read failed or not. Measured values are hardcoded with the intention of reading a 0."""
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if bl_volt > br_volt:
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debug.error("Read failure. Value 1 was read instead of 0.",1)
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def check_swing_from_vdd(self, bl_volt, br_volt):
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"""Checks difference on discharging bitline from VDD to see if it is within margin of the RBL height parameter."""
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if bl_volt < br_volt:
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discharge_volt = bl_volt
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else:
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discharge_volt = br_volt
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desired_bl_volt = tech.parameter["rbl_height_percentage"]*self.vdd_voltage
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debug.info(1, "Active bitline={:.3f}v, Desired bitline={:.3f}v".format(discharge_volt,desired_bl_volt))
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vdd_error_margin = .2 #20% of vdd margin for bitline, a little high for now.
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if abs(discharge_volt - desired_bl_volt) > vdd_error_margin*self.vdd_voltage:
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debug.warning("Bitline voltage is not within {}% Vdd margin. Delay chain/RBL could need resizing.".format(vdd_error_margin*100))
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def check_differential_swing(self, bl_volt, br_volt):
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"""This check looks at the difference between the bitline voltages. This needs to be large enough to prevent
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sensing errors."""
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bitline_swing = abs(bl_volt-br_volt)
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debug.info(1,"Bitline swing={:.3f}v".format(bitline_swing))
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vdd_error_margin = .2 #20% of vdd margin for bitline, a little high for now.
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if bitline_swing < vdd_error_margin*self.vdd_voltage:
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debug.warning("Bitline swing less than {}% Vdd margin. Sensing errors more likely to occur.".format(vdd_error_margin))
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def analyze(self, probe_address, probe_data, slews, loads):
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"""Measures the bitline swing of the differential bitlines (bl/br) at 50% s_en """
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self.set_probe(probe_address, probe_data)
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self.load=max(loads)
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self.slew=max(slews)
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read_port = self.read_ports[0] #only test the first read port
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bitline_swings = {}
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self.targ_read_ports = [read_port]
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self.targ_write_ports = [self.write_ports[0]]
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debug.info(1,"Bitline swing test: corner {}".format(self.corner))
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(success, results)=self.run_delay_simulation()
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debug.check(success, "Bitline Failed: period {}".format(self.period))
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debug.info(1,"Bitline values (voltages/delays):\n\t {}".format(results[read_port]))
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self.check_bitline_all_results(results)
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return results
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|
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@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import re
|
||||
import debug
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import sys,re,shutil,copy
|
||||
import debug
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import sys,re,shutil
|
||||
from design import design
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import os,sys,re
|
||||
import debug
|
||||
@@ -148,9 +148,9 @@ class lib:
|
||||
self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height))
|
||||
|
||||
#Build string of all control signals.
|
||||
control_str = 'CSb0' #assume at least 1 port
|
||||
control_str = 'csb0' #assume at least 1 port
|
||||
for i in range(1, self.total_port_num):
|
||||
control_str += ' & CSb{0}'.format(i)
|
||||
control_str += ' & csb{0}'.format(i)
|
||||
|
||||
# Leakage is included in dynamic when macro is enabled
|
||||
self.lib.write(" leakage_power () {\n")
|
||||
@@ -161,13 +161,17 @@ class lib:
|
||||
|
||||
|
||||
def write_units(self):
|
||||
""" Adds default units for time, voltage, current,..."""
|
||||
|
||||
""" Adds default units for time, voltage, current,...
|
||||
Valid values are 1mV, 10mV, 100mV, and 1V.
|
||||
For time: Valid values are 1ps, 10ps, 100ps, and 1ns.
|
||||
For power: Valid values are 1mW, 100uW (for 100mW), 10uW (for 10mW),
|
||||
1uW (for 1mW), 100nW, 10nW, 1nW, 100pW, 10pW, and 1pW.
|
||||
"""
|
||||
self.lib.write(" time_unit : \"1ns\" ;\n")
|
||||
self.lib.write(" voltage_unit : \"1v\" ;\n")
|
||||
self.lib.write(" voltage_unit : \"1V\" ;\n")
|
||||
self.lib.write(" current_unit : \"1mA\" ;\n")
|
||||
self.lib.write(" resistance_unit : \"1kohm\" ;\n")
|
||||
self.lib.write(" capacitive_load_unit(1 ,fF) ;\n")
|
||||
self.lib.write(" capacitive_load_unit(1, pF) ;\n")
|
||||
self.lib.write(" leakage_power_unit : \"1mW\" ;\n")
|
||||
self.lib.write(" pulling_resistance_unit :\"1kohm\" ;\n")
|
||||
self.lib.write(" operating_conditions(OC){\n")
|
||||
@@ -239,7 +243,9 @@ class lib:
|
||||
self.lib.write(" variable_1 : input_net_transition;\n")
|
||||
self.lib.write(" variable_2 : total_output_net_capacitance;\n")
|
||||
self.write_index(1,self.slews)
|
||||
self.write_index(2,self.loads)
|
||||
# Dividing by 1000 to all cap values since output of .sp is in fF,
|
||||
# and it needs to be in pF for Innovus.
|
||||
self.write_index(2,self.loads/1000)
|
||||
self.lib.write(" }\n\n")
|
||||
|
||||
CONS = ["CONSTRAINT_TABLE"]
|
||||
@@ -327,8 +333,8 @@ class lib:
|
||||
self.lib.write(" bus_type : DATA; \n")
|
||||
self.lib.write(" direction : output; \n")
|
||||
# This is conservative, but limit to range that we characterized.
|
||||
self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads)))
|
||||
self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads)))
|
||||
self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads)/1000))
|
||||
self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads)/1000))
|
||||
self.lib.write(" memory_read(){ \n")
|
||||
self.lib.write(" address : ADDR{0}; \n".format(read_port))
|
||||
self.lib.write(" }\n")
|
||||
@@ -362,7 +368,7 @@ class lib:
|
||||
self.lib.write(" bus_type : DATA; \n")
|
||||
self.lib.write(" direction : input; \n")
|
||||
# This is conservative, but limit to range that we characterized.
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000))
|
||||
self.lib.write(" memory_write(){ \n")
|
||||
self.lib.write(" address : ADDR{0}; \n".format(write_port))
|
||||
self.lib.write(" clocked_on : clk{0}; \n".format(write_port))
|
||||
@@ -385,7 +391,7 @@ class lib:
|
||||
self.lib.write(" bus(ADDR{0}){{\n".format(port))
|
||||
self.lib.write(" bus_type : ADDR; \n")
|
||||
self.lib.write(" direction : input; \n")
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000))
|
||||
self.lib.write(" max_transition : {0};\n".format(self.slews[-1]))
|
||||
self.lib.write(" pin(ADDR{0}[{1}:0])".format(port,self.sram.addr_size-1))
|
||||
self.lib.write("{\n")
|
||||
@@ -398,15 +404,15 @@ class lib:
|
||||
def write_control_pins(self, port):
|
||||
""" Adds control pins timing results."""
|
||||
#The control pins are still to be determined. This is a placeholder for what could be.
|
||||
ctrl_pin_names = ["CSb{0}".format(port)]
|
||||
ctrl_pin_names = ["csb{0}".format(port)]
|
||||
if port in self.readwrite_ports:
|
||||
ctrl_pin_names.append("WEb{0}".format(port))
|
||||
ctrl_pin_names.append("web{0}".format(port))
|
||||
|
||||
for i in ctrl_pin_names:
|
||||
self.lib.write(" pin({0})".format(i))
|
||||
self.lib.write("{\n")
|
||||
self.lib.write(" direction : input; \n")
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000))
|
||||
self.write_FF_setuphold(port)
|
||||
self.lib.write(" }\n\n")
|
||||
|
||||
@@ -417,7 +423,7 @@ class lib:
|
||||
self.lib.write(" clock : true;\n")
|
||||
self.lib.write(" direction : input; \n")
|
||||
# FIXME: This depends on the clock buffer size in the control logic
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
|
||||
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000))
|
||||
|
||||
self.add_clk_control_power(port)
|
||||
|
||||
@@ -452,10 +458,10 @@ class lib:
|
||||
|
||||
if port in self.write_ports:
|
||||
if port in self.read_ports:
|
||||
web_name = " & !WEb{0}".format(port)
|
||||
web_name = " & !web{0}".format(port)
|
||||
avg_write_power = np.mean(self.char_port_results[port]["write1_power"] + self.char_port_results[port]["write0_power"])
|
||||
self.lib.write(" internal_power(){\n")
|
||||
self.lib.write(" when : \"!CSb{0} & clk{0}{1}\"; \n".format(port, web_name))
|
||||
self.lib.write(" when : \"!csb{0} & clk{0}{1}\"; \n".format(port, web_name))
|
||||
self.lib.write(" rise_power(scalar){\n")
|
||||
self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
|
||||
self.lib.write(" }\n")
|
||||
@@ -466,10 +472,10 @@ class lib:
|
||||
|
||||
if port in self.read_ports:
|
||||
if port in self.write_ports:
|
||||
web_name = " & WEb{0}".format(port)
|
||||
web_name = " & web{0}".format(port)
|
||||
avg_read_power = np.mean(self.char_port_results[port]["read1_power"] + self.char_port_results[port]["read0_power"])
|
||||
self.lib.write(" internal_power(){\n")
|
||||
self.lib.write(" when : \"!CSb{0} & !clk{0}{1}\"; \n".format(port, web_name))
|
||||
self.lib.write(" when : \"!csb{0} & !clk{0}{1}\"; \n".format(port, web_name))
|
||||
self.lib.write(" rise_power(scalar){\n")
|
||||
self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
|
||||
self.lib.write(" }\n")
|
||||
@@ -480,7 +486,7 @@ class lib:
|
||||
|
||||
# Have 0 internal power when disabled, this will be represented as leakage power.
|
||||
self.lib.write(" internal_power(){\n")
|
||||
self.lib.write(" when : \"CSb{0}\"; \n".format(port))
|
||||
self.lib.write(" when : \"csb{0}\"; \n".format(port))
|
||||
self.lib.write(" rise_power(scalar){\n")
|
||||
self.lib.write(" values(\"0\");\n")
|
||||
self.lib.write(" }\n")
|
||||
@@ -610,9 +616,9 @@ class lib:
|
||||
))
|
||||
|
||||
for port in self.all_ports:
|
||||
#CSb timings
|
||||
#csb timings
|
||||
datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format(
|
||||
"CSb{0}".format(port),
|
||||
"csb{0}".format(port),
|
||||
min(list(map(round_time,self.times["setup_times_LH"]))),
|
||||
max(list(map(round_time,self.times["setup_times_LH"]))),
|
||||
|
||||
@@ -649,9 +655,9 @@ class lib:
|
||||
for port in self.all_ports:
|
||||
if port in self.readwrite_ports:
|
||||
|
||||
#WEb timings
|
||||
#web timings
|
||||
datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format(
|
||||
"WEb{0}".format(port),
|
||||
"web{0}".format(port),
|
||||
min(list(map(round_time,self.times["setup_times_LH"]))),
|
||||
max(list(map(round_time,self.times["setup_times_LH"]))),
|
||||
|
||||
@@ -673,8 +679,8 @@ class lib:
|
||||
|
||||
# write dynamic power usage
|
||||
if port in self.read_ports:
|
||||
web_name = " & !WEb{0}".format(port)
|
||||
name = "!CSb{0} & clk{0}{1}".format(port, web_name)
|
||||
web_name = " & !web{0}".format(port)
|
||||
name = "!csb{0} & clk{0}{1}".format(port, web_name)
|
||||
read_write = 'Read'
|
||||
|
||||
datasheet.write("{0},{1},{2},{3},".format(
|
||||
@@ -686,8 +692,8 @@ class lib:
|
||||
))
|
||||
|
||||
if port in self.write_ports:
|
||||
web_name = " & WEb{0}".format(port)
|
||||
name = "!CSb{0} & !clk{0}{1}".format(port, web_name)
|
||||
web_name = " & web{0}".format(port)
|
||||
name = "!csb{0} & !clk{0}{1}".format(port, web_name)
|
||||
read_write = 'Write'
|
||||
|
||||
datasheet.write("{0},{1},{2},{3},".format(
|
||||
@@ -699,9 +705,9 @@ class lib:
|
||||
))
|
||||
|
||||
# write leakage power
|
||||
control_str = 'CSb0'
|
||||
control_str = 'csb0'
|
||||
for i in range(1, self.total_port_num):
|
||||
control_str += ' & CSb{0}'.format(i)
|
||||
control_str += ' & csb{0}'.format(i)
|
||||
|
||||
datasheet.write("{0},{1},{2},".format('leak', control_str, self.char_sram_results["leakage_power"]))
|
||||
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import debug
|
||||
from tech import drc, parameter, spice
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import debug
|
||||
from tech import drc, parameter, spice
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import sys,re,shutil
|
||||
import debug
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import sys
|
||||
import tech
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import sys,re,shutil
|
||||
from design import design
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
"""
|
||||
This file generates simple spice cards for simulation. There are
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import debug
|
||||
from math import log
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import sys,re,shutil
|
||||
import debug
|
||||
|
||||
Reference in New Issue
Block a user