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@@ -1,9 +1,9 @@
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# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import contact
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import design
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@@ -36,6 +36,7 @@ class pbitcell(design.design):
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self.create_netlist()
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# We must always create the bitcell layout because some transistor sizes in the other netlists depend on it
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self.create_layout()
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self.add_boundary()
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def create_netlist(self):
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self.add_pins()
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@@ -79,9 +80,7 @@ class pbitcell(design.design):
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# in netlist_only mode, calling offset_all_coordinates or translate_all will not be possible
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# this function is not needed to calculate the dimensions of pbitcell in netlist_only mode though
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if not OPTS.netlist_only:
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self.offset_all_coordinates()
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gnd_overlap = vector(0, 0.5*contact.well.width)
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self.translate_all(gnd_overlap)
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self.translate_all(vector(self.leftmost_xpos, self.botmost_ypos))
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def add_pins(self):
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@@ -143,7 +142,8 @@ class pbitcell(design.design):
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def add_modules(self):
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""" Determine size of transistors and add ptx modules """
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# if there are any read/write ports, then the inverter nmos is sized based the number of read/write ports
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# if there are any read/write ports,
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# then the inverter nmos is sized based the number of read/write ports
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if(self.num_rw_ports > 0):
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inverter_nmos_width = self.num_rw_ports*parameter["6T_inv_nmos_size"]
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inverter_pmos_width = parameter["6T_inv_pmos_size"]
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@@ -151,7 +151,8 @@ class pbitcell(design.design):
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write_nmos_width = parameter["6T_access_size"]
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read_nmos_width = 2*parameter["6T_inv_pmos_size"]
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# if there are no read/write ports, then the inverter nmos is statically sized for the dual port case
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# if there are no read/write ports,
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# then the inverter nmos is statically sized for the dual port case
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else:
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inverter_nmos_width = 2*parameter["6T_inv_pmos_size"]
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inverter_pmos_width = parameter["6T_inv_pmos_size"]
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@@ -185,14 +186,21 @@ class pbitcell(design.design):
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def calculate_spacing(self):
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""" Calculate transistor spacings """
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# calculate metal contact extensions over transistor active
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readwrite_nmos_contact_extension = 0.5*(self.readwrite_nmos.active_contact.height - self.readwrite_nmos.active_height)
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write_nmos_contact_extension = 0.5*(self.write_nmos.active_contact.height - self.write_nmos.active_height)
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read_nmos_contact_extension = 0.5*(self.read_nmos.active_contact.height - self.read_nmos.active_height)
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max_contact_extension = max(readwrite_nmos_contact_extension, write_nmos_contact_extension, read_nmos_contact_extension)
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readwrite_nmos_contact_extension = 0.5*(self.readwrite_nmos.active_contact.height \
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- self.readwrite_nmos.active_height)
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write_nmos_contact_extension = 0.5*(self.write_nmos.active_contact.height \
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- self.write_nmos.active_height)
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read_nmos_contact_extension = 0.5*(self.read_nmos.active_contact.height \
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- self.read_nmos.active_height)
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max_contact_extension = max(readwrite_nmos_contact_extension,
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write_nmos_contact_extension,
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read_nmos_contact_extension)
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# y-offset for the access transistor's gate contact
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self.gate_contact_yoffset = max_contact_extension + self.m2_space + 0.5*max(contact.poly.height, contact.m1m2.height)
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self.gate_contact_yoffset = max_contact_extension + self.m2_space \
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+ 0.5*max(contact.poly.height, contact.m1m2.height)
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# y-position of access transistors
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self.port_ypos = self.m1_space + 0.5*contact.m1m2.height + self.gate_contact_yoffset
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@@ -201,8 +209,10 @@ class pbitcell(design.design):
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self.inverter_nmos_ypos = self.port_ypos
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# spacing between ports (same for read/write and write ports)
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self.bitline_offset = -0.5*self.readwrite_nmos.active_width + 0.5*contact.m1m2.height + self.m2_space + self.m2_width
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m2_constraint = self.bitline_offset + self.m2_space + 0.5*contact.m1m2.height - 0.5*self.readwrite_nmos.active_width
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self.bitline_offset = -0.5*self.readwrite_nmos.active_width + 0.5*contact.m1m2.height \
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+ self.m2_space + self.m2_width
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m2_constraint = self.bitline_offset + self.m2_space + 0.5*contact.m1m2.height \
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- 0.5*self.readwrite_nmos.active_width
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self.write_port_spacing = max(self.active_space, self.m1_space, m2_constraint)
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self.read_port_spacing = self.bitline_offset + self.m2_space
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@@ -224,11 +234,11 @@ class pbitcell(design.design):
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+ 1.5*contact.poly.width
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# spacing between wordlines (and gnd)
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self.rowline_spacing = self.m1_space + contact.m1m2.width
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self.rowline_offset = -0.5*self.m1_width
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self.m1_offset = -0.5*self.m1_width
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# spacing for vdd
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implant_constraint = max(inverter_pmos_contact_extension, 0) + 2*self.implant_enclose_active + 0.5*(contact.well.width - self.m1_width)
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implant_constraint = max(inverter_pmos_contact_extension, 0) + 2*self.implant_enclose_active \
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+ 0.5*(contact.well.width - self.m1_width)
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metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space
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self.vdd_offset = max(implant_constraint, metal1_constraint) + 0.5*self.m1_width
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@@ -238,8 +248,10 @@ class pbitcell(design.design):
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def calculate_postions(self):
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""" Calculate positions that describe the edges and dimensions of the cell """
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self.botmost_ypos = -0.5*self.m1_width - self.total_ports*self.rowline_spacing
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self.topmost_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset
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self.botmost_ypos = self.m1_offset - self.total_ports*self.m1_pitch
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self.topmost_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \
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+ self.inverter_gap + self.inverter_pmos.active_height \
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+ self.vdd_offset
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self.leftmost_xpos = -0.5*self.inverter_to_inverter_spacing - self.inverter_nmos.active_width \
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- self.num_rw_ports*(self.readwrite_nmos.active_width + self.write_port_spacing) \
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@@ -249,9 +261,9 @@ class pbitcell(design.design):
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self.width = -2*self.leftmost_xpos
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self.height = self.topmost_ypos - self.botmost_ypos
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self.center_ypos = 0.5*(self.topmost_ypos + self.botmost_ypos)
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def create_storage(self):
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"""
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Creates the crossed coupled inverters that act as storage for the bitcell.
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@@ -309,13 +321,15 @@ class pbitcell(design.design):
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width=contact.active.second_layer_width)
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# add contacts to connect gate poly to drain/source metal1 (to connect Q to Q_bar)
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contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x + 0.5*contact.poly.height, self.cross_couple_upper_ypos)
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contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x + 0.5*contact.poly.height,
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self.cross_couple_upper_ypos)
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self.add_via_center(layers=("poly", "contact", "metal1"),
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offset=contact_offset_left,
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directions=("H","H"))
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contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x - 0.5*contact.poly.height, self.cross_couple_lower_ypos)
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contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x - 0.5*contact.poly.height,
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self.cross_couple_lower_ypos)
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self.add_via_center(layers=("poly", "contact", "metal1"),
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offset=contact_offset_right,
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directions=("H","H"))
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@@ -330,21 +344,21 @@ class pbitcell(design.design):
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def route_rails(self):
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""" Adds gnd and vdd rails and connects them to the inverters """
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# Add rails for vdd and gnd
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gnd_ypos = self.rowline_offset - self.total_ports*self.rowline_spacing
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gnd_ypos = self.m1_offset - self.total_ports*self.m1_pitch
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self.gnd_position = vector(0, gnd_ypos)
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self.add_rect_center(layer="metal1",
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offset=self.gnd_position,
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width=self.width,
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height=self.m1_width)
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width=self.width)
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self.add_power_pin("gnd", vector(0,gnd_ypos))
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vdd_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset
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vdd_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \
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+ self.inverter_gap + self.inverter_pmos.active_height \
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+ self.vdd_offset
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self.vdd_position = vector(0, vdd_ypos)
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self.add_rect_center(layer="metal1",
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offset=self.vdd_position,
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width=self.width,
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height=self.m1_width)
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width=self.width)
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self.add_power_pin("vdd", vector(0,vdd_ypos))
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def create_readwrite_ports(self):
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@@ -395,13 +409,12 @@ class pbitcell(design.design):
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self.readwrite_nmos_right[k].place(offset=[right_readwrite_transistor_xpos, self.port_ypos])
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# add pin for RWWL
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rwwl_ypos = self.rowline_offset - k*self.rowline_spacing
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rwwl_ypos = self.m1_offset - k*self.m1_pitch
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self.rwwl_positions[k] = vector(0, rwwl_ypos)
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self.add_layout_pin_rect_center(text=self.rw_wl_names[k],
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layer="metal1",
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offset=self.rwwl_positions[k],
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width=self.width,
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height=self.m1_width)
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width=self.width)
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# add pins for RWBL and RWBR
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rwbl_xpos = left_readwrite_transistor_xpos - self.bitline_offset + 0.5*self.m2_width
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@@ -411,7 +424,8 @@ class pbitcell(design.design):
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offset=self.rwbl_positions[k],
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height=self.height)
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rwbr_xpos = right_readwrite_transistor_xpos + self.readwrite_nmos.active_width + self.bitline_offset - 0.5*self.m2_width
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rwbr_xpos = right_readwrite_transistor_xpos + self.readwrite_nmos.active_width \
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+ self.bitline_offset - 0.5*self.m2_width
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self.rwbr_positions[k] = vector(rwbr_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.rw_br_names[k],
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layer="metal2",
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@@ -470,13 +484,13 @@ class pbitcell(design.design):
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self.write_nmos_right[k].place(offset=[right_write_transistor_xpos, self.port_ypos])
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# add pin for WWL
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wwl_ypos = rwwl_ypos = self.rowline_offset - self.num_rw_ports*self.rowline_spacing - k*self.rowline_spacing
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wwl_ypos = rwwl_ypos = self.m1_offset - self.num_rw_ports*self.m1_pitch \
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- k*self.m1_pitch
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self.wwl_positions[k] = vector(0, wwl_ypos)
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self.add_layout_pin_rect_center(text=self.w_wl_names[k],
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layer="metal1",
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offset=self.wwl_positions[k],
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width=self.width,
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height=self.m1_width)
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width=self.width)
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# add pins for WBL and WBR
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wbl_xpos = left_write_transistor_xpos - self.bitline_offset + 0.5*self.m2_width
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@@ -486,7 +500,8 @@ class pbitcell(design.design):
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offset=self.wbl_positions[k],
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height=self.height)
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wbr_xpos = right_write_transistor_xpos + self.write_nmos.active_width + self.bitline_offset - 0.5*self.m2_width
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wbr_xpos = right_write_transistor_xpos + self.write_nmos.active_width + self.bitline_offset \
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- 0.5*self.m2_width
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self.wbr_positions[k] = vector(wbr_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.w_br_names[k],
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layer="metal2",
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@@ -567,13 +582,13 @@ class pbitcell(design.design):
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self.read_nmos_right[k].place(offset=[right_read_transistor_xpos+overlap_offset, self.port_ypos])
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# add pin for RWL
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rwl_ypos = rwwl_ypos = self.rowline_offset - self.num_rw_ports*self.rowline_spacing - self.num_w_ports*self.rowline_spacing - k*self.rowline_spacing
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rwl_ypos = rwwl_ypos = self.m1_offset - self.num_rw_ports*self.m1_pitch \
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- self.num_w_ports*self.m1_pitch - k*self.m1_pitch
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self.rwl_positions[k] = vector(0, rwl_ypos)
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self.add_layout_pin_rect_center(text=self.r_wl_names[k],
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layer="metal1",
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offset=self.rwl_positions[k],
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width=self.width,
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height=self.m1_width)
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width=self.width)
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# add pins for RBL and RBR
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rbl_xpos = left_read_transistor_xpos - self.bitline_offset + 0.5*self.m2_width
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@@ -583,7 +598,8 @@ class pbitcell(design.design):
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offset=self.rbl_positions[k],
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height=self.height)
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rbr_xpos = right_read_transistor_xpos + self.read_port_width + self.bitline_offset - 0.5*self.m2_width
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rbr_xpos = right_read_transistor_xpos + self.read_port_width + self.bitline_offset \
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- 0.5*self.m2_width
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self.rbr_positions[k] = vector(rbr_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.r_br_names[k],
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layer="metal2",
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@@ -741,12 +757,14 @@ class pbitcell(design.design):
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def route_read_access(self):
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""" Routes read access transistors to the storage component of the bitcell """
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# add poly to metal1 contacts for gates of the inverters
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left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - self.poly_to_polycontact - 0.5*contact.poly.width, self.cross_couple_upper_ypos)
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left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - self.poly_to_polycontact - 0.5*contact.poly.width,
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self.cross_couple_upper_ypos)
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self.add_via_center(layers=("poly", "contact", "metal1"),
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offset=left_storage_contact,
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directions=("H","H"))
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right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + self.poly_to_polycontact + 0.5*contact.poly.width, self.cross_couple_upper_ypos)
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right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + self.poly_to_polycontact + 0.5*contact.poly.width,
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self.cross_couple_upper_ypos)
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self.add_via_center(layers=("poly", "contact", "metal1"),
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offset=right_storage_contact,
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directions=("H","H"))
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Hunter Nichols