mirror of https://github.com/VLSIDA/OpenRAM.git
Move spare wen_dff to the right by spare columns
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bc3de9db05
commit
4df02dad67
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@ -109,18 +109,20 @@ class sram_1bank(sram_base):
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self.wmask_dff_insts[port].place(wmask_pos[port])
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self.wmask_dff_insts[port].place(wmask_pos[port])
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x_offset = self.wmask_dff_insts[port].rx()
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x_offset = self.wmask_dff_insts[port].rx()
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# Add spare write enable flops to the right of write mask flops
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# Add the data flops below the write mask flops.
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data_pos[port] = vector(x_offset,
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y_offset)
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self.data_dff_insts[port].place(data_pos[port])
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x_offset = self.data_dff_insts[port].rx()
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# Add spare write enable flops to the right of data flops since the spare columns
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# will be on the right
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if self.num_spare_cols:
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if self.num_spare_cols:
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spare_wen_pos[port] = vector(x_offset,
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spare_wen_pos[port] = vector(x_offset,
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y_offset)
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y_offset)
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self.spare_wen_dff_insts[port].place(spare_wen_pos[port])
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self.spare_wen_dff_insts[port].place(spare_wen_pos[port])
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x_offset = self.spare_wen_dff_insts[port].rx()
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x_offset = self.spare_wen_dff_insts[port].rx()
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# Add the data flops below the write mask flops.
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data_pos[port] = vector(x_offset,
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y_offset)
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self.data_dff_insts[port].place(data_pos[port])
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else:
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else:
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wmask_pos[port] = vector(x_offset, y_offset)
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wmask_pos[port] = vector(x_offset, y_offset)
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data_pos[port] = vector(x_offset, y_offset)
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data_pos[port] = vector(x_offset, y_offset)
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@ -159,6 +161,14 @@ class sram_1bank(sram_base):
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col_addr_pos[port] = vector(x_offset, y_offset)
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col_addr_pos[port] = vector(x_offset, y_offset)
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if port in self.write_ports:
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if port in self.write_ports:
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# Add spare write enable flops to the right of the data flops since the spare
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# columns will be on the left
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if self.num_spare_cols:
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spare_wen_pos[port] = vector(x_offset - self.spare_wen_dff_insts[port].width,
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y_offset)
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self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX")
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x_offset = self.spare_wen_dff_insts[port].lx()
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if self.write_size:
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if self.write_size:
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# Add the write mask flops below the write mask AND array.
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# Add the write mask flops below the write mask AND array.
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wmask_pos[port] = vector(x_offset - self.wmask_dff_insts[port].width,
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wmask_pos[port] = vector(x_offset - self.wmask_dff_insts[port].width,
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@ -166,18 +176,12 @@ class sram_1bank(sram_base):
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self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
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self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
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x_offset = self.wmask_dff_insts[port].lx()
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x_offset = self.wmask_dff_insts[port].lx()
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# Add spare write enable flops to the right of write mask flops
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if self.num_spare_cols:
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spare_wen_pos[port] = vector(x_offset - self.spare_wen_dff_insts[port].width,
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y_offset)
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self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX")
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x_offset = self.spare_wen_dff_insts[port].lx()
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# Add the data flops below the write mask flops.
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# Add the data flops below the write mask flops.
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data_pos[port] = vector(x_offset - self.data_dff_insts[port].width,
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data_pos[port] = vector(x_offset - self.data_dff_insts[port].width,
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y_offset)
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y_offset)
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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else:
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else:
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wmask_pos[port] = vector(x_offset, y_offset)
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wmask_pos[port] = vector(x_offset, y_offset)
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data_pos[port] = vector(x_offset, y_offset)
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data_pos[port] = vector(x_offset, y_offset)
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@ -360,20 +364,9 @@ class sram_1bank(sram_base):
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route_map.extend(list(zip(bank_pins, dff_pins)))
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route_map.extend(list(zip(bank_pins, dff_pins)))
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if self.num_wmasks > 0 and port in self.write_ports:
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if self.num_wmasks > 0 and port in self.write_ports:
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vertical_layer = "m4"
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layer_stack = self.m3_stack
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layer_stack = self.m3_stack
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else:
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else:
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vertical_layer = "m2"
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layer_stack = self.m1_stack
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layer_stack = self.m1_stack
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for (pin1, pin2) in route_map:
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if pin1.layer != vertical_layer:
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self.add_via_stack_center(from_layer=pin1.layer,
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to_layer=vertical_layer,
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offset=pin1.center())
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if pin2.layer != vertical_layer:
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self.add_via_stack_center(from_layer=pin2.layer,
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to_layer=vertical_layer,
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offset=pin2.center())
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if port == 0:
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if port == 0:
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offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
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offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
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@ -580,6 +573,7 @@ class sram_1bank(sram_base):
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self.create_horizontal_channel_route(netlist=route_map,
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self.create_horizontal_channel_route(netlist=route_map,
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offset=offset,
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offset=offset,
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layer_stack=self.m1_stack)
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layer_stack=self.m1_stack)
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def route_spare_wen_dff(self):
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def route_spare_wen_dff(self):
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""" Connect the output of the spare write enable flops to the spare write drivers """
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""" Connect the output of the spare write enable flops to the spare write drivers """
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# This is where the channel will start (y-dimension at least)
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# This is where the channel will start (y-dimension at least)
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