mirror of https://github.com/VLSIDA/OpenRAM.git
Add redundant implant for s8
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@ -11,7 +11,7 @@ from tech import drc, layer
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from vector import vector
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from vector import vector
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from sram_factory import factory
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from sram_factory import factory
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import logical_effort
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import logical_effort
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from utils import round_to_grid
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from globals import OPTS
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class single_level_column_mux(pgate.pgate):
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class single_level_column_mux(pgate.pgate):
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@ -119,6 +119,9 @@ class single_level_column_mux(pgate.pgate):
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offset=nmos_upper_position)
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offset=nmos_upper_position)
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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if OPTS.tech_name == "sky130":
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self.add_implants()
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def connect_poly(self):
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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""" Connect the poly gate of the two pass transistors """
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@ -190,6 +193,19 @@ class single_level_column_mux(pgate.pgate):
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self.add_path(self.col_mux_stack[2],
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self.add_path(self.col_mux_stack[2],
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[br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()])
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[br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()])
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def add_implants(self):
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"""
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Add top-to-bottom implants for adjacency issues in s8.
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"""
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# Route to the bottom
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ll = (self.nmos_lower.ll() - vector(2 * [self.implant_enclose_active])).scale(1, 0)
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# Don't route to the top
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ur = self.nmos_upper.ur() + vector(self.implant_enclose_active, 0)
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self.add_rect("nimplant",
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ll,
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ur.x - ll.x,
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ur.y - ll.y)
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def add_pn_wells(self):
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def add_pn_wells(self):
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"""
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"""
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Add a well and implant over the whole cell. Also, add the
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Add a well and implant over the whole cell. Also, add the
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