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OpenRAM
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Moved via in write driver up for 2 port.

This commit is contained in:
jsowash 2019-09-03 15:14:41 -07:00
parent abb86c338b
commit 4c40804b8f
2 changed files with 6 additions and 3 deletions
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5
compiler/sram/sram_1bank.py
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@ -383,7 +383,10 @@ class sram_1bank(sram_base):
bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
if self.write_size:
for x in bank_names:
pin_offset = self.bank_inst.get_pin(x).bc()
if port % 2:
pin_offset = self.bank_inst.get_pin(x).uc()
else:
pin_offset = self.bank_inst.get_pin(x).bc()
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=pin_offset)
self.add_via_center(layers=("metal2", "via2", "metal3"),

4
compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
View File

@ -17,8 +17,8 @@ from sram_factory import factory
import debug
# @unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class psram_1bank_2mux_1rw_1w_test(openram_test):
# @unittest.skip("SKIPPING psram_1bank_2mux_1rw_1w_wmask_test, multiport layout not complete")
class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))