Share nominal temperature and voltage. Nominal instead of typical.

compiler/base/hierarchy_spice.py

@@ -392,7 +392,7 @@ class spice():
         """Returns delay increase due to voltage.
            Implemented as linear factor based off nominal voltage.
         """
-        return tech.spice['vdd_nominal']/voltage
+        return tech.spice["nom_supply_voltage"]/voltage
         
     def get_temp_delay_factor(self, temp):
         """Returns delay increase due to temperature (in C).
@@ -400,11 +400,11 @@ class spice():
         """
         #Some portions of equation condensed (phi_t = k*T/q for T in Kelvin) in mV
         #(k/q)/100 = .008625, The division 100 simplifies the conversion from C to K and mV to V
-        thermal_voltage_nom = .008625*tech.spice["temp_nominal"]
+        thermal_voltage_nom = 0.008625*tech.spice["nom_temperature"]
-        thermal_voltage = .008625*temp
+        thermal_voltage = 0.008625*temp
-        vthresh = (tech.spice["v_threshold_typical"]+2*(thermal_voltage-thermal_voltage_nom))
+        vthresh = (tech.spice["nom_threshold"]+2*(thermal_voltage-thermal_voltage_nom))
         #Calculate effect on Vdd-Vth. The current vdd is not used here. A separate vdd factor is calculated.
-        return (tech.spice['vdd_nominal'] - tech.spice["v_threshold_typical"])/(tech.spice['vdd_nominal']-vthresh)
+        return (tech.spice["nom_supply_voltage"] - tech.spice["nom_threshold"])/(tech.spice["nom_supply_voltage"]-vthresh)
 
     def return_delay(self, delay, slew):
         return delay_data(delay, slew)

compiler/characterizer/simulation.py

@@ -48,8 +48,8 @@ class simulation():
         self.slew = tech.spice["rise_time"]*2
         self.load = tech.spice["dff_in_cap"]*4
 
-        self.v_high = self.vdd_voltage - tech.spice["v_threshold_typical"]
+        self.v_high = self.vdd_voltage - tech.spice["nom_threshold"]
-        self.v_low = tech.spice["v_threshold_typical"]        
+        self.v_low = tech.spice["nom_threshold"]        
         self.gnd_voltage = 0
         
     def create_signal_names(self):

technology/freepdk45/tech/tech.py

@@ -304,9 +304,7 @@ spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
 spice["nom_temperature"] = 25        # Nominal temperature (celcius)
 
 # analytical delay parameters
-spice["vdd_nominal"] = 1.0    # Typical Threshold voltage in Volts
+spice["nom_threshold"] = 0.4    # Typical Threshold voltage in Volts
-spice["temp_nominal"] = 25.0   # Typical Threshold voltage in Volts
-spice["v_threshold_typical"] = 0.4    # Typical Threshold voltage in Volts
 spice["wire_unit_r"] = 0.075     # Unit wire resistance in ohms/square
 spice["wire_unit_c"] = 0.64      # Unit wire capacitance ff/um^2
 spice["min_tx_drain_c"] = 0.7    # Minimum transistor drain capacitance in ff

technology/scn3me_subm/tech/tech.py

@@ -219,8 +219,6 @@ spice["nmos"]="n"
 spice["pmos"]="p"
 # This is a map of corners to model files
 SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
-# FIXME: Uncomment when we have the new spice models
-#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
 spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
                         "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
                         "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
@@ -243,10 +241,8 @@ spice["temperatures"] = [0, 25, 100]  # Temperature corners (celcius)
 spice["nom_temperature"] = 25        # Nominal temperature (celcius)
 
 # analytical delay parameters
+spice["nom_threshold"] = 1.3   # Typical Threshold voltage in Volts
 # FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
-spice["vdd_nominal"] = 5.0    # Typical Threshold voltage in Volts
-spice["temp_nominal"] = 25.0   # Typical Threshold voltage in Volts
-spice["v_threshold_typical"] = 1.3   # Typical Threshold voltage in Volts
 spice["wire_unit_r"] = 0.075    # Unit wire resistance in ohms/square
 spice["wire_unit_c"] = 0.64     # Unit wire capacitance ff/um^2
 spice["min_tx_drain_c"] = 0.7   # Minimum transistor drain capacitance in ff

technology/scn4m_subm/tech/tech.py

@@ -247,8 +247,6 @@ spice["nmos"]="n"
 spice["pmos"]="p"
 # This is a map of corners to model files
 SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
-# FIXME: Uncomment when we have the new spice models
-#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
 spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
                         "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
                         "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
@@ -271,10 +269,8 @@ spice["temperatures"] = [0, 25, 100]  # Temperature corners (celcius)
 spice["nom_temperature"] = 25        # Nominal temperature (celcius)
 
 # analytical delay parameters
+spice["nom_threshold"] = 1.3   # Nominal Threshold voltage in Volts
 # FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
-spice["vdd_nominal"] = 5.0    # Typical Threshold voltage in Volts
-spice["temp_nominal"] = 25.0   # Typical Threshold voltage in Volts
-spice["v_threshold_typical"] = 1.3   # Typical Threshold voltage in Volts
 spice["wire_unit_r"] = 0.075    # Unit wire resistance in ohms/square
 spice["wire_unit_c"] = 0.64     # Unit wire capacitance ff/um^2
 spice["min_tx_drain_c"] = 0.7   # Minimum transistor drain capacitance in ff