mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 16:31:08 +02:00
Share nominal temperature and voltage. Nominal instead of typical.
This commit is contained in:
@@ -48,8 +48,8 @@ class simulation():
|
||||
self.slew = tech.spice["rise_time"]*2
|
||||
self.load = tech.spice["dff_in_cap"]*4
|
||||
|
||||
self.v_high = self.vdd_voltage - tech.spice["v_threshold_typical"]
|
||||
self.v_low = tech.spice["v_threshold_typical"]
|
||||
self.v_high = self.vdd_voltage - tech.spice["nom_threshold"]
|
||||
self.v_low = tech.spice["nom_threshold"]
|
||||
self.gnd_voltage = 0
|
||||
|
||||
def create_signal_names(self):
|
||||
|
||||
Reference in New Issue
Block a user