mirror of https://github.com/VLSIDA/OpenRAM.git
top level boundary fixes
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7fe5ed5c41
commit
4c34a54d32
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@ -77,8 +77,6 @@ class rom_bank(design):
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if not OPTS.is_unit_test:
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if not OPTS.is_unit_test:
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print_time("Placement", datetime.datetime.now(), start_time)
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print_time("Placement", datetime.datetime.now(), start_time)
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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self.add_boundary()
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start_time = datetime.datetime.now()
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start_time = datetime.datetime.now()
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@ -93,6 +91,17 @@ class rom_bank(design):
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self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
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self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
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print_time("Verification", datetime.datetime.now(), start_time)
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print_time("Verification", datetime.datetime.now(), start_time)
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def add_boundary(self):
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ll = self.find_lowest_coords()
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m1_offset = self.m1_width
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self.translate_all(vector(0, ll.y))
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ur = self.find_highest_coords()
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ur = vector(ur.x, ur.y)
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super().add_boundary(vector(0, 0), ur)
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self.width = ur.x
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self.height = ur.y
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def route_layout(self):
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def route_layout(self):
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self.route_decode_outputs()
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self.route_decode_outputs()
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self.route_precharge()
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self.route_precharge()
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