mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed supply end-row via problem by restricting placement
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parent
f5e68c5c32
commit
4c25bb09df
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@ -32,6 +32,14 @@ def increment_set(curset, direct):
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return newset
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return newset
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def remove_border(curset, direct):
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"""
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Remove the cells on a given border.
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"""
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border = get_border(curset, direct)
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curset.difference_update(border)
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def get_upper_right(curset):
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def get_upper_right(curset):
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ur = None
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ur = None
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for p in curset:
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for p in curset:
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@ -89,6 +89,8 @@ class supply_router(router):
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self.route_pins_to_rails(gnd_name, remaining_gnd_pin_indices)
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self.route_pins_to_rails(gnd_name, remaining_gnd_pin_indices)
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#self.write_debug_gds("debug_pin_routes.gds",stop_program=True)
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#self.write_debug_gds("debug_pin_routes.gds",stop_program=True)
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#self.write_debug_gds("final.gds")
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return True
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return True
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@ -112,7 +114,6 @@ class supply_router(router):
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# if no overlap, add it to the complex route pins
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# if no overlap, add it to the complex route pins
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remaining_pins.append(index)
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remaining_pins.append(index)
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else:
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else:
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print("Overlap!",index)
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self.create_simple_overlap_enclosure(pin_name, common_set)
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self.create_simple_overlap_enclosure(pin_name, common_set)
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return remaining_pins
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return remaining_pins
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@ -131,19 +132,15 @@ class supply_router(router):
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supply_overlap = next_set & supply_tracks
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supply_overlap = next_set & supply_tracks
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wire_overlap = next_set & supply_wire_tracks
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wire_overlap = next_set & supply_wire_tracks
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print("EXAMINING: ",start_set,len(start_set),len(supply_overlap),len(wire_overlap),direct)
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# If the rail overlap is the same, we are done, since we connected to the actual wire
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# If the rail overlap is the same, we are done, since we connected to the actual wire
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if len(wire_overlap)==len(start_set):
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if len(wire_overlap)==len(start_set):
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print("HIT RAIL", wire_overlap)
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new_set = start_set | wire_overlap
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new_set = start_set | wire_overlap
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# If the supply overlap is the same, keep expanding unti we hit the wire or move out of the rail region
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# If the supply overlap is the same, keep expanding unti we hit the wire or move out of the rail region
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elif len(supply_overlap)==len(start_set):
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elif len(supply_overlap)==len(start_set):
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print("RECURSE", supply_overlap)
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recurse_set = self.recurse_simple_overlap_enclosure(pin_name, supply_overlap, direct)
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recurse_set = self.recurse_simple_overlap_enclosure(pin_name, supply_overlap, direct)
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new_set = start_set | supply_overlap | recurse_set
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new_set = start_set | supply_overlap | recurse_set
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else:
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else:
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# If we got no next set, we are done, can't expand!
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# If we got no next set, we are done, can't expand!
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print("NO MORE OVERLAP", supply_overlap)
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new_set = set()
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new_set = set()
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return new_set
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return new_set
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@ -190,15 +187,43 @@ class supply_router(router):
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connections = set()
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connections = set()
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via_areas = []
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via_areas = []
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for i1,r1 in enumerate(all_rails):
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for i1,r1 in enumerate(all_rails):
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# We need to move this rail to the other layer for the intersection to work
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# Only consider r1 horizontal rails
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e = next(iter(r1))
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e = next(iter(r1))
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newz = (e.z+1)%2
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if e.z==1:
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new_r1 = {vector3d(i.x,i.y,newz) for i in r1}
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continue
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# We need to move this rail to the other layer for the z indices to match
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# during the intersection. This also makes a copy.
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new_r1 = {vector3d(i.x,i.y,1) for i in r1}
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# If horizontal, subtract off the left/right track to prevent end of rail via
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#ll = grid_utils.get_lower_left(new_r1)
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#ur = grid_utils.get_upper_right(new_r1)
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grid_utils.remove_border(new_r1, direction.EAST)
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grid_utils.remove_border(new_r1, direction.WEST)
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for i2,r2 in enumerate(all_rails):
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for i2,r2 in enumerate(all_rails):
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# Never compare to yourself
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if i1==i2:
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if i1==i2:
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continue
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continue
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overlap = new_r1 & r2
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# Only consider r2 vertical rails
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e = next(iter(r2))
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if e.z==0:
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continue
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# Need to maek a copy to consider via overlaps to ignore the end-caps
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new_r2 = r2.copy()
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grid_utils.remove_border(new_r2, direction.NORTH)
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grid_utils.remove_border(new_r2, direction.SOUTH)
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# Determine if we hhave sufficient overlap and, if so,
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# remember:
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# the indices to determine a rail is connected to another
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# the overlap area for placement of a via
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overlap = new_r1 & new_r2
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if len(overlap) >= self.supply_rail_wire_width**2:
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if len(overlap) >= self.supply_rail_wire_width**2:
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debug.info(2,"Via overlap {0} {1} {2}".format(len(overlap),self.supply_rail_wire_width**2,overlap))
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connections.add(i1)
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connections.add(i1)
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connections.add(i2)
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connections.add(i2)
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via_areas.append(overlap)
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via_areas.append(overlap)
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@ -210,9 +235,11 @@ class supply_router(router):
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center = (ll + ur).scale(0.5,0.5,0)
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center = (ll + ur).scale(0.5,0.5,0)
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self.add_via(center,self.rail_track_width)
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self.add_via(center,self.rail_track_width)
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# Determien which indices were not connected to anything above
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all_indices = set([x for x in range(len(self.supply_rails[name]))])
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all_indices = set([x for x in range(len(self.supply_rails[name]))])
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missing_indices = all_indices ^ connections
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missing_indices = all_indices ^ connections
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# Go through and remove those disconnected indices
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# (No via was added, so that doesn't need to be removed)
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for rail_index in missing_indices:
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for rail_index in missing_indices:
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ll = grid_utils.get_lower_left(all_rails[rail_index])
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ll = grid_utils.get_lower_left(all_rails[rail_index])
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ur = grid_utils.get_upper_right(all_rails[rail_index])
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ur = grid_utils.get_upper_right(all_rails[rail_index])
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@ -220,8 +247,8 @@ class supply_router(router):
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self.supply_rails[name].pop(rail_index)
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self.supply_rails[name].pop(rail_index)
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self.supply_rail_wires[name].pop(rail_index)
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self.supply_rail_wires[name].pop(rail_index)
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# Make the supply rails into a big giant set of grids
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# Make the supply rails into a big giant set of grids for easy blockages.
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# Must be done after determine which ones are connected)
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# Must be done after we determine which ones are connected.
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self.create_supply_track_set(name)
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self.create_supply_track_set(name)
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@ -381,6 +408,7 @@ class supply_router(router):
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if len(wave_path)>=4*self.rail_track_width:
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if len(wave_path)>=4*self.rail_track_width:
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grid_set = wave_path.get_grids()
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grid_set = wave_path.get_grids()
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self.supply_rails[name].append(grid_set)
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self.supply_rails[name].append(grid_set)
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start_wire_index = self.supply_rail_space_width
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start_wire_index = self.supply_rail_space_width
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end_wire_index = self.supply_rail_width - self.supply_rail_space_width
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end_wire_index = self.supply_rail_width - self.supply_rail_space_width
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wire_set = wave_path.get_wire_grids(start_wire_index,end_wire_index)
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wire_set = wave_path.get_wire_grids(start_wire_index,end_wire_index)
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