Thin-cell decoder changes.

Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case

compiler/tests/02_library_lvs_test.py

@@ -35,7 +35,7 @@ class library_lvs_test(openram_test):
                 debug.error("Missing GDS file {}".format(gds_name))
             if not os.path.isfile(sp_name):
                 lvs_errors += 1
-                debug.error("Missing SPICE file {}".format(gds_name))
+                debug.error("Missing SPICE file {}".format(sp_name))
             drc_errors += verify.run_drc(name, gds_name)
             lvs_errors += verify.run_lvs(f, gds_name, sp_name)
 

compiler/tests/04_pand2_dec_test.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class pand2_dec_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        global verify
+        import verify
+
+        import pand2_dec
+
+        debug.info(2, "Testing pand2 gate 4x")
+        a = pand2_dec.pand2_dec(name="pand2x4", size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_pand3_dec_test.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class pand3_dec_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        global verify
+        import verify
+
+        import pand3_dec
+
+        debug.info(2, "Testing pand3 gate 4x")
+        a = pand3_dec.pand3_dec(name="pand3x4", size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_pand4_dec_test.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class pand3_dec_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        global verify
+        import verify
+
+        import pand3_dec
+
+        debug.info(2, "Testing pand3 gate 4x")
+        a = pand3_dec.pand3_dec(name="pand3x4", size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_pdriver_test.py

@@ -32,13 +32,13 @@ class pdriver_test(openram_test):
         c = factory.create(module_type="pdriver", fanout = 50)
         self.local_check(c)
         
-        d = factory.create(module_type="pdriver", fanout = 50, neg_polarity = True)
+        d = factory.create(module_type="pdriver", fanout = 50, inverting = True)
         self.local_check(d)
         
         e = factory.create(module_type="pdriver", fanout = 64)
         self.local_check(e)
         
-        f = factory.create(module_type="pdriver", fanout = 64, neg_polarity = True)
+        f = factory.create(module_type="pdriver", fanout = 64, inverting = True)
         self.local_check(f)
 
         globals.end_openram()

compiler/tests/04_pinv_dec_1x_test.py

@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class pinv_dec_1x_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        debug.info(2, "Checking 1x size decoder inverter")
+        tx = factory.create(module_type="pinv_dec", size=1)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_wordline_driver_test.py

@@ -25,7 +25,7 @@ class wordline_driver_test(openram_test):
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
-        tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
+        tx = factory.create(module_type="wordline_driver")
         self.local_check(tx)
 
         globals.end_openram()

compiler/tests/06_hierarchical_decoder_test.py

@@ -21,11 +21,17 @@ class hierarchical_decoder_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+
         # Checks 2x4 and 2-input NAND decoder
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
         self.local_check(a)
-        
+
         # Checks 2x4 and 2-input NAND decoder with non-power-of-two
         debug.info(1, "Testing 17 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=17)

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -21,7 +21,12 @@ class hierarchical_predecode2x4_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        # checking hierarchical precode 2x4 for single port
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -21,7 +21,12 @@ class hierarchical_predecode3x8_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        # checking hierarchical precode 3x8 for single port
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)

compiler/tests/06_hierarchical_predecode4x16_test.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+@unittest.skip("SKIPPING hierarchical_predecode4x16_test")
+class hierarchical_predecode4x16_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+
+        debug.info(1, "Testing sample for hierarchy_predecode4x16")
+        a = factory.create(module_type="hierarchical_predecode4x16")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/08_wordline_driver_array_pbitcell_test.py

@@ -15,9 +15,8 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 04_driver_test")
 
-class wordline_driver_pbitcell_test(openram_test):
+class wordline_driver_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -31,7 +30,7 @@ class wordline_driver_pbitcell_test(openram_test):
 
         factory.reset()
         debug.info(2, "Checking driver (multi-port case)")
-        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
+        tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64)
         self.local_check(tx)
 
         globals.end_openram()

compiler/tests/08_wordline_driver_array_test.py

@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class wordline_driver_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check wordline driver for single port
+        debug.info(2, "Checking driver")
+        tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/18_port_data_1rw_1r_test.py

@@ -20,10 +20,10 @@ class port_data_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.num_rw_ports = 0
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
+        OPTS.num_w_ports = 0
 
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_test.py

@@ -25,28 +25,28 @@ class single_bank_test(openram_test):
         c = sram_config(word_size=4,
                         num_words=16)
 
-        # c.words_per_row=1
-        # factory.reset()
-        # c.recompute_sizes()
-        # debug.info(1, "No column mux")
-        # a = factory.create("bank", sram_config=c)
-        # self.local_check(a)
+        c.words_per_row=1
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
 
-        # c.num_words=32
-        # c.words_per_row=2
-        # factory.reset()
-        # c.recompute_sizes()
-        # debug.info(1, "Two way column mux")
-        # a = factory.create("bank", sram_config=c)
-        # self.local_check(a)
+        c.num_words=32
+        c.words_per_row=2
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Two way column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
 
-        # c.num_words=64
-        # c.words_per_row=4
-        # factory.reset()
-        # c.recompute_sizes()
-        # debug.info(1, "Four way column mux")
-        # a = factory.create("bank", sram_config=c)
-        # self.local_check(a)
+        c.num_words=64
+        c.words_per_row=4
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Four way column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
 
         c.word_size=2
         c.num_words=128

compiler/tests/testutils.py

@@ -60,6 +60,7 @@ class openram_test(unittest.TestCase):
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
                 #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 debug.warning("DRC failed but LVS passed: {}".format(a.name))
+                #self.fail("DRC failed but LVS passed: {}".format(a.name))
             elif drc_result != 0:
                 #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))