mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-01 18:48:10 +02:00
Thin-cell decoder changes.
Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
This commit is contained in:
mrg
@@ -13,7 +13,7 @@ from sram_factory import factory
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class pand2(pgate.pgate):
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"""
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This is a simple buffer used for driving loads.
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This is an AND (or NAND) with configurable drive strength.
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"""
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def __init__(self, name, size=1, height=None, vertical=False, add_wells=True):
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debug.info(1, "Creating pand2 {}".format(name))
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@@ -17,13 +17,13 @@ class pdriver(pgate.pgate):
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sized for driving a load.
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"""
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def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None, add_wells=True):
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def __init__(self, name, inverting=False, fanout=0, size_list=None, height=None, add_wells=True):
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debug.info(1, "creating pdriver {}".format(name))
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self.stage_effort = 3
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self.height = height
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self.neg_polarity = neg_polarity
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self.inverting = inverting
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self.size_list = size_list
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self.fanout = fanout
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@@ -31,8 +31,8 @@ class pdriver(pgate.pgate):
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debug.error("Either fanout or size list must be specified.", -1)
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if self.size_list and self.fanout != 0:
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debug.error("Cannot specify both size_list and fanout.", -1)
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if self.size_list and self.neg_polarity:
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debug.error("Cannot specify both size_list and neg_polarity.", -1)
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if self.size_list and self.inverting:
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debug.error("Cannot specify both size_list and inverting.", -1)
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# Creates the netlist and layout
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pgate.pgate.__init__(self, name, height, add_wells)
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@@ -47,9 +47,9 @@ class pdriver(pgate.pgate):
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int(round(self.fanout ** (1 / self.stage_effort))))
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# Increase the number of stages if we need to fix polarity
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if self.neg_polarity and (self.num_stages % 2 == 0):
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if self.inverting and (self.num_stages % 2 == 0):
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self.num_stages += 1
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elif not self.neg_polarity and (self.num_stages % 2):
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elif not self.inverting and (self.num_stages % 2):
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self.num_stages += 1
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self.size_list = []
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@@ -44,7 +44,6 @@ class pgate(design.design):
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self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer))
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# This is the space from a S/D contact to the supply rail
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# Assume the contact starts at the active edge
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contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space
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# This is a poly-to-poly of a flipped cell
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poly_to_poly_gate_space = self.poly_extend_active + self.poly_space
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@@ -0,0 +1,217 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import contact
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import pinv
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import debug
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from tech import drc, parameter
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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if(OPTS.tech_name == "s8"):
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from tech import nmos_bins, pmos_bins, accuracy_requirement
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class pinv_dec(pinv.pinv):
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"""
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This is another version of pinv but with layout for the decoder.
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Other stuff is the same (netlist, sizes, etc.)
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"""
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def __init__(self, name, size=1, beta=parameter["beta"], height=None, add_wells=True):
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debug.info(2,
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"creating pinv_dec structure {0} with size of {1}".format(name,
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size))
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if not height:
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b = factory.create(module_type="bitcell")
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self.cell_height = b.height
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else:
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self.cell_height = height
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# Inputs to cells are on input layer
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# Outputs from cells are on output layer
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if OPTS.tech_name == "s8":
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self.supply_layer = "m1"
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else:
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self.supply_layer = "m2"
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pinv.pinv.__init__(self, name, size, beta, self.cell_height, add_wells)
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def determine_tx_mults(self):
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"""
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Determines the number of fingers needed to achieve the size within
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the height constraint. This may fail if the user has a tight height.
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"""
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# This is always 1 tx, because we have horizontal transistors.
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self.tx_mults = 1
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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if OPTS.tech_name == "s8":
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(self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
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(self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)
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return
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# Over-ride the route input gate to call the horizontal version.
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# Other top-level netlist and layout functions are not changed.
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def route_input_gate(self, pmos_inst, nmos_inst, ypos, name, position="left", directions=None):
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"""
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Route the input gate to the left side of the cell for access.
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Position is actually ignored and is left to be compatible with the pinv.
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"""
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nmos_gate_pin = nmos_inst.get_pin("G")
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pmos_gate_pin = pmos_inst.get_pin("G")
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# Check if the gates are aligned and give an error if they aren't!
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if nmos_gate_pin.ll().y != pmos_gate_pin.ll().y:
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self.gds_write("unaliged_gates.gds")
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debug.check(nmos_gate_pin.ll().y == pmos_gate_pin.ll().y,
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"Connecting unaligned gates not supported. See unaligned_gates.gds.")
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# Pick point on the left of NMOS and up to PMOS
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nmos_gate_pos = nmos_gate_pin.rc()
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pmos_gate_pos = pmos_gate_pin.lc()
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self.add_path("poly", [nmos_gate_pos, pmos_gate_pos])
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# Center is completely symmetric.
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contact_width = contact.poly_contact.width
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contact_offset = nmos_gate_pin.lc() \
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- vector(self.poly_extend_active + 0.5 * contact_width, 0)
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via = self.add_via_stack_center(from_layer="poly",
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to_layer=self.route_layer,
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offset=contact_offset,
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directions=directions)
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self.add_path("poly", [contact_offset, nmos_gate_pin.lc()])
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self.add_layout_pin_rect_center(text=name,
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layer=self.route_layer,
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offset=contact_offset,
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width=via.mod.second_layer_width,
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height=via.mod.second_layer_height)
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def determine_width(self):
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self.width = self.pmos_inst.rx() + self.well_extend_active
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def extend_wells(self):
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""" Extend bottom to top for each well. """
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from tech import layer
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if "pwell" in layer:
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ll = self.nmos_inst.ll() - self.nmos_inst.mod.active_offset
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ur = self.nmos_inst.ur() + self.nmos_inst.mod.active_offset
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self.add_rect(layer="pwell",
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offset=ll,
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width=ur.x - ll.x,
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height=self.height - ll.y)
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if "nwell" in layer:
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ll = self.pmos_inst.ll() - self.pmos_inst.mod.active_offset
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ur = self.pmos_inst.ur() + self.pmos_inst.mod.active_offset
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self.add_rect(layer="nwell",
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offset=ll - vector(self.nwell_enclose_active, 0),
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width=ur.x - ll.x + self.nwell_enclose_active,
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height=self.height - ll.y + 2 * self.nwell_enclose_active)
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def place_ptx(self):
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"""
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"""
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# offset so that the input contact is over from the left edge by poly spacing
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x_offset = self.nmos.active_offset.y + contact.poly_contact.width + self.poly_space
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# center the transistor in the y-dimension
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y_offset = self.nmos.width + self.active_space
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self.nmos_pos = vector(x_offset, y_offset)
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self.nmos_inst.place(self.nmos_pos)
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self.nmos_inst.place(self.nmos_pos,
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rotate=270)
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# place PMOS so it is half a poly spacing down from the top
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xoffset = self.nmos_inst.height + 2 * self.poly_extend_active + 2 * self.well_extend_active + drc("pwell_to_nwell")
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self.pmos_pos = self.nmos_pos + vector(xoffset, 0)
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self.pmos_inst.place(self.pmos_pos,
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rotate=270)
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# Output position will be in between the PMOS and NMOS drains
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pmos_drain_pos = self.pmos_inst.get_pin("D").center()
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nmos_drain_pos = self.nmos_inst.get_pin("D").center()
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self.output_pos = vector(0.5 * (pmos_drain_pos.x + nmos_drain_pos.x), nmos_drain_pos.y)
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def route_outputs(self):
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"""
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Route the output (drains) together.
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Optionally, routes output to edge.
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"""
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# Get the drain pin
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nmos_drain_pin = self.nmos_inst.get_pin("D")
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# Pick point at right most of NMOS and connect over to PMOS
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nmos_drain_pos = nmos_drain_pin.lc()
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right_side = vector(self.width, nmos_drain_pos.y)
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self.add_layout_pin_segment_center("Z",
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self.route_layer,
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nmos_drain_pos,
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right_side)
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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source_pos = self.pmos_inst.get_pin("S").center()
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contact_pos = vector(source_pos.x, self.height)
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self.nwell_contact = self.add_via_center(layers=self.active_stack,
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offset=contact_pos,
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implant_type="n",
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well_type="n")
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self.add_via_stack_center(offset=contact_pos,
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from_layer=self.active_stack[2],
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to_layer=self.supply_layer)
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source_pos = self.nmos_inst.get_pin("S").center()
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contact_pos = vector(source_pos.x, self.height)
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self.pwell_contact= self.add_via_center(layers=self.active_stack,
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offset=contact_pos,
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implant_type="p",
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well_type="p")
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self.add_via_stack_center(offset=contact_pos,
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from_layer=self.active_stack[2],
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to_layer=self.supply_layer)
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def route_supply_rails(self):
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pin = self.nmos_inst.get_pin("S")
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source_pos = pin.center()
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bottom_pos = source_pos.scale(1, 0)
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top_pos = bottom_pos + vector(0, self.height)
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self.add_layout_pin_segment_center("gnd",
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self.supply_layer,
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start=bottom_pos,
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end=top_pos)
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pin = self.pmos_inst.get_pin("S")
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source_pos = pin.center()
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bottom_pos = source_pos.scale(1, 0)
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top_pos = bottom_pos + vector(0, self.height)
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self.add_layout_pin_segment_center("vdd",
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self.supply_layer,
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start=bottom_pos,
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end=top_pos)
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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source_pos = self.nmos_inst.get_pin("S").center()
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self.add_via_stack_center(offset=source_pos,
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from_layer=self.route_layer,
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to_layer=self.supply_layer)
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source_pos = self.pmos_inst.get_pin("S").center()
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self.add_via_stack_center(offset=source_pos,
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from_layer=self.route_layer,
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to_layer=self.supply_layer)
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@@ -212,7 +212,10 @@ class pnand3(pgate.pgate):
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pmos_drain_bottom = self.pmos1_inst.get_pin("D").by()
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self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space
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# This is a more compact offset, but the bottom one works better in the decoders to "center" the pins
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# in the height of the gates
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self.inputA_yoffset = self.output_yoffset - 0.5 * self.route_layer_width - self.route_layer_space
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# self.inputA_yoffset = self.output_yoffset - self.m1_pitch
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self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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@@ -386,10 +386,12 @@ class ptx(design.design):
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well_ll = center_pos - vector(0.5 * self.well_width,
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0.5 * self.well_height)
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if well_name in layer:
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self.add_rect(layer=well_name,
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offset=well_ll,
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width=self.well_width,
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height=self.well_height)
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well = self.add_rect(layer=well_name,
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offset=well_ll,
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width=self.well_width,
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height=self.well_height)
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setattr(self, well_name, well)
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if "vtg" in layer:
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self.add_rect(layer="vtg",
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offset=well_ll,
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@@ -0,0 +1,155 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from vector import vector
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import design
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from sram_factory import factory
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from globals import OPTS
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from tech import layer
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class wordline_driver(design.design):
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"""
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This is an AND (or NAND) with configurable drive strength to drive the wordlines.
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It is matched to the bitcell height.
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"""
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def __init__(self, name, size=1, height=None):
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debug.info(1, "Creating wordline_driver {}".format(name))
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self.add_comment("size: {}".format(size))
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design.design.__init__(self, name)
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if height is None:
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b = factory.create(module_type="bitcell")
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self.height = b.height
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else:
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self.height = height
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self.size = size
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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if OPTS.tech_name == "s8":
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self.nand = factory.create(module_type="nand2_dec")
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self.height = self.nand.height
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else:
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self.nand = factory.create(module_type="nand2_dec",
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height=self.height)
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self.driver = factory.create(module_type="inv_dec",
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size=self.size,
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height=self.nand.height)
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self.add_mod(self.nand)
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self.add_mod(self.driver)
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def create_layout(self):
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self.width = self.nand.width + self.driver.width
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.place_insts()
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self.route_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="wld_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"])
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self.driver_inst = self.add_inst(name="wl_driver",
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mod=self.driver)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0, 0))
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# Add INV to the right
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self.driver_inst.place(offset=vector(self.nand_inst.rx(), 0))
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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if OPTS.tech_name == "s8":
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for name in ["vdd", "gnd"]:
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for inst in [self.nand_inst, self.driver_inst]:
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self.copy_layout_pin(inst, name)
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else:
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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y_offset = self.height
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self.add_layout_pin_rect_center(text="vdd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, y_offset),
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width=self.width)
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def route_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.driver_inst.get_pin("A")
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if OPTS.tech_name == "s8":
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mid1_point = vector(a2_pin.cx(), z1_pin.cy())
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else:
|
||||
mid1_point = vector(z1_pin.cx(), a2_pin.cy())
|
||||
self.add_path(self.route_layer,
|
||||
[z1_pin.center(), mid1_point, a2_pin.center()])
|
||||
|
||||
def add_layout_pins(self):
|
||||
pin = self.driver_inst.get_pin("Z")
|
||||
self.add_layout_pin_rect_center(text="Z",
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in ["A", "B"]:
|
||||
pin = self.nand_inst.get_pin(pin_name)
|
||||
self.add_layout_pin_rect_center(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A or B -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.driver.get_cin()
|
||||
stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
|
||||
stage2 = self.driver.get_stage_effort(external_cout, stage1.is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
Reference in New Issue
Block a user