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Thin-cell decoder changes.
Add hard decoder gates (nand, inv, pnan) Add conditions for routing using LI layer in s8. Generalize bus layers for decoders. Move custom cells to own directory. Fixed via directions, etc. Add 4x16 hierarchical decoder and test case
This commit is contained in:
mrg
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import GDS, layer, spice, parameter
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from tech import cell_properties as props
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import utils
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class dff(design.design):
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"""
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Memory address flip-flop
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"""
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if not props.dff.use_custom_ports:
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pin_names = ["D", "Q", "clk", "vdd", "gnd"]
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type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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clk_pin = "clk"
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else:
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pin_names = props.dff.custom_port_list
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type_list = props.dff.custom_type_list
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clk_pin = props.dff.clk_pin
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(width, height) = utils.get_libcell_size("dff",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"])
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def __init__(self, name="dff"):
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design.design.__init__(self, name)
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self.width = dff.width
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self.height = dff.height
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self.pin_map = dff.pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["dff_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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from tech import parameter
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c_load = load
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c_para = spice["dff_out_cap"]#ff
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transition_prob = 0.5
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return transition_prob*(c_load + c_para)
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
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return parameter["dff_clk_cin"]
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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@@ -0,0 +1,80 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import GDS, layer, spice, parameter
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import logical_effort
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import utils
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import debug
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class inv_dec(design.design):
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"""
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INV for address decoders.
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"""
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pin_names = ["A", "Z", "vdd", "gnd"]
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type_list = ["INPUT", "OUTPUT", "POWER", "GROUND"]
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(width, height) = utils.get_libcell_size("inv_dec",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "inv_dec", GDS["unit"])
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def __init__(self, name="inv_dec", height=None):
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design.design.__init__(self, name)
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self.width = inv_dec.width
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self.height = inv_dec.height
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self.pin_map = inv_dec.pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["inv_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""
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Return the capacitance of the gate connection in generic capacitive
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units relative to the minimum width of a transistor
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"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
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Input inverted by this stage.
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"""
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parasitic_delay = 1
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return logical_effort.logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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@@ -0,0 +1,77 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import GDS, layer, spice, parameter
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import logical_effort
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import utils
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class nand2_dec(design.design):
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"""
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2-input NAND decoder for address decoders.
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"""
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pin_names = ["A", "B", "Z", "vdd", "gnd"]
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type_list = ["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
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(width, height) = utils.get_libcell_size("nand2_dec",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "nand2_dec", GDS["unit"])
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def __init__(self, name="nand2_dec", height=None):
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design.design.__init__(self, name)
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self.width = nand2_dec.width
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self.height = nand2_dec.height
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self.pin_map = nand2_dec.pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nand2_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1875
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""Return the relative input capacitance of a single input"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
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Input inverted by this stage.
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"""
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parasitic_delay = 2
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return logical_effort.logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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@@ -0,0 +1,77 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import GDS, layer, spice, parameter
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import logical_effort
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import utils
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class nand3_dec(design.design):
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"""
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3-input NAND decoder for address decoders.
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"""
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pin_names = ["A", "B", "C", "Z", "vdd", "gnd"]
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type_list = ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
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(width, height) = utils.get_libcell_size("nand3_dec",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "nand3_dec", GDS["unit"])
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def __init__(self, name="nand3_dec", height=None):
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design.design.__init__(self, name)
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self.width = nand3_dec.width
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self.height = nand3_dec.height
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self.pin_map = nand3_dec.pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nand3_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1875
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""Return the relative input capacitance of a single input"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
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Input inverted by this stage.
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"""
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parasitic_delay = 2
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return logical_effort.logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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@@ -0,0 +1,77 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import GDS, layer, spice, parameter
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import logical_effort
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import utils
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class nand4_dec(design.design):
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"""
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2-input NAND decoder for address decoders.
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"""
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pin_names = ["A", "B", "C", "D", "Z", "vdd", "gnd"]
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type_list = ["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
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(width, height) = utils.get_libcell_size("nand4_dec",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "nand4_dec", GDS["unit"])
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def __init__(self, name="nand4_dec", height=None):
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design.design.__init__(self, name)
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self.width = nand4_dec.width
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self.height = nand4_dec.height
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self.pin_map = nand4_dec.pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nand4_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1875
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""Return the relative input capacitance of a single input"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
|
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Input inverted by this stage.
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"""
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parasitic_delay = 2
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return logical_effort.logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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@@ -0,0 +1,138 @@
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# See LICENSE for licensing information.
|
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
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# All rights reserved.
|
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#
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import debug
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from vector import vector
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import pgate
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from sram_factory import factory
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from globals import OPTS
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class pand2_dec(pgate.pgate):
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"""
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This is an AND with configurable drive strength.
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"""
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def __init__(self, name, size=1, height=None, add_wells=True):
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debug.info(1, "Creating pand2_dec {}".format(name))
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self.add_comment("size: {}".format(size))
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self.size = size
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pgate.pgate.__init__(self, name, height, add_wells)
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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if OPTS.tech_name == "s8":
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self.nand = factory.create(module_type="nand2_dec")
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else:
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self.nand = factory.create(module_type="nand2_dec",
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height=self.height)
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self.inv = factory.create(module_type="inv_dec",
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height=self.height,
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size=self.size)
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self.add_mod(self.nand)
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self.add_mod(self.inv)
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def create_layout(self):
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self.width = self.nand.width + self.inv.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="pand2_dec_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"])
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self.inv_inst = self.add_inst(name="pand2_dec_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0, 0))
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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if OPTS.tech_name == "s8":
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for name in ["vdd", "gnd"]:
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for inst in [self.nand_inst, self.inv_inst]:
|
||||
self.copy_layout_pin(inst, name)
|
||||
else:
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=self.route_layer,
|
||||
offset=vector(0.5 * self.width, 0),
|
||||
width=self.width)
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=self.route_layer,
|
||||
offset=vector(0.5 * self.width, self.height),
|
||||
width=self.width)
|
||||
|
||||
def add_wires(self):
|
||||
# nand Z to inv A
|
||||
z1_pin = self.nand_inst.get_pin("Z")
|
||||
a2_pin = self.inv_inst.get_pin("A")
|
||||
if OPTS.tech_name == "s8":
|
||||
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
|
||||
else:
|
||||
mid1_point = vector(z1_pin.cx(), a2_pin.cy())
|
||||
self.add_path(self.route_layer,
|
||||
[z1_pin.center(), mid1_point, a2_pin.center()])
|
||||
|
||||
def add_layout_pins(self):
|
||||
pin = self.inv_inst.get_pin("Z")
|
||||
self.add_layout_pin_rect_center(text="Z",
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in ["A", "B"]:
|
||||
pin = self.nand_inst.get_pin(pin_name)
|
||||
self.add_layout_pin_rect_center(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A or B -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv.get_cin()
|
||||
stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
@@ -0,0 +1,149 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import debug
|
||||
from vector import vector
|
||||
import pgate
|
||||
from sram_factory import factory
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class pand3_dec(pgate.pgate):
|
||||
"""
|
||||
This is an AND with configurable drive strength.
|
||||
"""
|
||||
def __init__(self, name, size=1, height=None, add_wells=True):
|
||||
debug.info(1, "Creating pand3_dec {}".format(name))
|
||||
self.add_comment("size: {}".format(size))
|
||||
|
||||
self.size = size
|
||||
|
||||
pgate.pgate.__init__(self, name, height, add_wells)
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_pins()
|
||||
self.create_modules()
|
||||
self.create_insts()
|
||||
|
||||
def create_modules(self):
|
||||
if OPTS.tech_name == "s8":
|
||||
self.nand = factory.create(module_type="nand3_dec")
|
||||
else:
|
||||
self.nand = factory.create(module_type="nand3_dec",
|
||||
height=self.height)
|
||||
|
||||
self.inv = factory.create(module_type="inv_dec",
|
||||
height=self.height,
|
||||
size=self.size)
|
||||
|
||||
self.add_mod(self.nand)
|
||||
self.add_mod(self.inv)
|
||||
|
||||
def create_layout(self):
|
||||
self.width = self.nand.width + self.inv.width
|
||||
|
||||
self.place_insts()
|
||||
self.add_wires()
|
||||
self.add_layout_pins()
|
||||
self.route_supply_rails()
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
self.add_pin("A", "INPUT")
|
||||
self.add_pin("B", "INPUT")
|
||||
self.add_pin("C", "INPUT")
|
||||
self.add_pin("Z", "OUTPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def create_insts(self):
|
||||
self.nand_inst = self.add_inst(name="pand3_dec_nand",
|
||||
mod=self.nand)
|
||||
self.connect_inst(["A", "B", "C", "zb_int", "vdd", "gnd"])
|
||||
|
||||
self.inv_inst = self.add_inst(name="pand3_dec_inv",
|
||||
mod=self.inv)
|
||||
self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
|
||||
|
||||
def place_insts(self):
|
||||
# Add NAND to the right
|
||||
self.nand_inst.place(offset=vector(0, 0))
|
||||
|
||||
# Add INV to the right
|
||||
self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
|
||||
|
||||
def route_supply_rails(self):
|
||||
""" Add vdd/gnd rails to the top, (middle), and bottom. """
|
||||
if OPTS.tech_name == "s8":
|
||||
for name in ["vdd", "gnd"]:
|
||||
for inst in [self.nand_inst, self.inv_inst]:
|
||||
self.copy_layout_pin(inst, name)
|
||||
else:
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=self.route_layer,
|
||||
offset=vector(0.5 * self.width, 0),
|
||||
width=self.width)
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=self.route_layer,
|
||||
offset=vector(0.5 * self.width, self.height),
|
||||
width=self.width)
|
||||
|
||||
def add_wires(self):
|
||||
# nand Z to inv A
|
||||
z1_pin = self.nand_inst.get_pin("Z")
|
||||
a2_pin = self.inv_inst.get_pin("A")
|
||||
if OPTS.tech_name == "s8":
|
||||
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
|
||||
else:
|
||||
mid1_point = vector(z1_pin.cx(), a2_pin.cy())
|
||||
self.add_path(self.route_layer,
|
||||
[z1_pin.center(), mid1_point, a2_pin.center()])
|
||||
|
||||
def add_layout_pins(self):
|
||||
pin = self.inv_inst.get_pin("Z")
|
||||
self.add_layout_pin_rect_center(text="Z",
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in ["A", "B", "C"]:
|
||||
pin = self.nand_inst.get_pin(pin_name)
|
||||
self.add_layout_pin_rect_center(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
def analytical_delay(self, corner, slew, load=0.0):
|
||||
""" Calculate the analytical delay of DFF-> INV -> INV """
|
||||
nand_delay = self.nand.analytical_delay(corner,
|
||||
slew=slew,
|
||||
load=self.inv.input_load())
|
||||
inv_delay = self.inv.analytical_delay(corner,
|
||||
slew=nand_delay.slew,
|
||||
load=load)
|
||||
return nand_delay + inv_delay
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A or B -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv.get_cin()
|
||||
stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
@@ -0,0 +1,149 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import debug
|
||||
from vector import vector
|
||||
import pgate
|
||||
from sram_factory import factory
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class pand4_dec(pgate.pgate):
|
||||
"""
|
||||
This is an AND with configurable drive strength.
|
||||
"""
|
||||
def __init__(self, name, size=1, height=None, add_wells=True):
|
||||
debug.info(1, "Creating pand4_dec {}".format(name))
|
||||
self.add_comment("size: {}".format(size))
|
||||
|
||||
self.size = size
|
||||
|
||||
pgate.pgate.__init__(self, name, height, add_wells)
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_pins()
|
||||
self.create_modules()
|
||||
self.create_insts()
|
||||
|
||||
def create_modules(self):
|
||||
if OPTS.tech_name == "s8":
|
||||
self.nand = factory.create(module_type="nand4_dec")
|
||||
else:
|
||||
self.nand = factory.create(module_type="nand4_dec",
|
||||
height=self.height)
|
||||
|
||||
self.inv = factory.create(module_type="inv_dec",
|
||||
size=self.size)
|
||||
|
||||
self.add_mod(self.nand)
|
||||
self.add_mod(self.inv)
|
||||
|
||||
def create_layout(self):
|
||||
self.width = self.nand.width + self.inv.width
|
||||
|
||||
self.place_insts()
|
||||
self.add_wires()
|
||||
self.add_layout_pins()
|
||||
self.route_supply_rails()
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
self.add_pin("A", "INPUT")
|
||||
self.add_pin("B", "INPUT")
|
||||
self.add_pin("C", "INPUT")
|
||||
self.add_pin("D", "INPUT")
|
||||
self.add_pin("Z", "OUTPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def create_insts(self):
|
||||
self.nand_inst = self.add_inst(name="pand4_dec_nand",
|
||||
mod=self.nand)
|
||||
self.connect_inst(["A", "B", "C", "D", "zb_int", "vdd", "gnd"])
|
||||
|
||||
self.inv_inst = self.add_inst(name="pand4_dec_inv",
|
||||
mod=self.inv)
|
||||
self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
|
||||
|
||||
def place_insts(self):
|
||||
# Add NAND to the right
|
||||
self.nand_inst.place(offset=vector(0, 0))
|
||||
|
||||
# Add INV to the right
|
||||
self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
|
||||
|
||||
def route_supply_rails(self):
|
||||
""" Add vdd/gnd rails to the top, (middle), and bottom. """
|
||||
if OPTS.tech_name == "s8":
|
||||
for name in ["vdd", "gnd"]:
|
||||
for inst in [self.nand_inst, self.inv_inst]:
|
||||
self.copy_layout_pin(inst, name)
|
||||
else:
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=self.route_layer,
|
||||
offset=vector(0.5 * self.width, 0),
|
||||
width=self.width)
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=self.route_layer,
|
||||
offset=vector(0.5 * self.width, self.height),
|
||||
width=self.width)
|
||||
|
||||
def add_wires(self):
|
||||
# nand Z to inv A
|
||||
z1_pin = self.nand_inst.get_pin("Z")
|
||||
a2_pin = self.inv_inst.get_pin("A")
|
||||
if OPTS.tech_name == "s8":
|
||||
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
|
||||
else:
|
||||
mid1_point = vector(z1_pin.cx(), a2_pin.cy())
|
||||
self.add_path(self.route_layer,
|
||||
[z1_pin.center(), mid1_point, a2_pin.center()])
|
||||
|
||||
def add_layout_pins(self):
|
||||
pin = self.inv_inst.get_pin("Z")
|
||||
self.add_layout_pin_rect_center(text="Z",
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in ["A", "B", "C"]:
|
||||
pin = self.nand_inst.get_pin(pin_name)
|
||||
self.add_layout_pin_rect_center(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
def analytical_delay(self, corner, slew, load=0.0):
|
||||
""" Calculate the analytical delay of DFF-> INV -> INV """
|
||||
nand_delay = self.nand.analytical_delay(corner,
|
||||
slew=slew,
|
||||
load=self.inv.input_load())
|
||||
inv_delay = self.inv.analytical_delay(corner,
|
||||
slew=nand_delay.slew,
|
||||
load=load)
|
||||
return nand_delay + inv_delay
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A or B -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv.get_cin()
|
||||
stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import debug
|
||||
import design
|
||||
import utils
|
||||
from tech import GDS,layer
|
||||
|
||||
class tri_gate(design.design):
|
||||
"""
|
||||
This module implements the tri gate cell used in the design forS
|
||||
bit-line isolation. It is a hand-made cell, so the layout and
|
||||
netlist should be available in the technology library.
|
||||
"""
|
||||
|
||||
pin_names = ["in", "out", "en", "en_bar", "vdd", "gnd"]
|
||||
type_list = ["INPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
|
||||
(width,height) = utils.get_libcell_size("tri_gate", GDS["unit"], layer["boundary"])
|
||||
pin_map = utils.get_libcell_pins(pin_names, "tri_gate", GDS["unit"])
|
||||
|
||||
unique_id = 1
|
||||
|
||||
def __init__(self, name=""):
|
||||
if name=="":
|
||||
name = "tri{0}".format(tri_gate.unique_id)
|
||||
tri_gate.unique_id += 1
|
||||
design.design.__init__(self, name)
|
||||
debug.info(2, "Create tri_gate")
|
||||
|
||||
self.width = tri_gate.width
|
||||
self.height = tri_gate.height
|
||||
self.pin_map = tri_gate.pin_map
|
||||
self.add_pin_types(self.type_list)
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Returns dynamic and leakage power. Results in nW"""
|
||||
#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
|
||||
total_power = self.return_power()
|
||||
return total_power
|
||||
|
||||
def get_cin(self):
|
||||
return 9*spice["min_tx_gate_c"]
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
"""Adds edges based on inputs/outputs. Overrides base class function."""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
@@ -0,0 +1,68 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import debug
|
||||
import design
|
||||
import utils
|
||||
from globals import OPTS
|
||||
from tech import GDS,layer
|
||||
from tech import cell_properties as props
|
||||
|
||||
class write_driver(design.design):
|
||||
"""
|
||||
Tristate write driver to be active during write operations only.
|
||||
This module implements the write driver cell used in the design. It
|
||||
is a hand-made cell, so the layout and netlist should be available in
|
||||
the technology library.
|
||||
"""
|
||||
|
||||
pin_names = [props.write_driver.pin.din,
|
||||
props.write_driver.pin.bl,
|
||||
props.write_driver.pin.br,
|
||||
props.write_driver.pin.en,
|
||||
props.write_driver.pin.vdd,
|
||||
props.write_driver.pin.gnd]
|
||||
|
||||
type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
|
||||
if not OPTS.netlist_only:
|
||||
(width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
|
||||
pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
|
||||
else:
|
||||
(width,height) = (0,0)
|
||||
pin_map = []
|
||||
|
||||
def __init__(self, name):
|
||||
design.design.__init__(self, name)
|
||||
debug.info(2, "Create write_driver")
|
||||
|
||||
self.width = write_driver.width
|
||||
self.height = write_driver.height
|
||||
self.pin_map = write_driver.pin_map
|
||||
self.add_pin_types(self.type_list)
|
||||
|
||||
def get_bl_names(self):
|
||||
return props.write_driver.pin.bl
|
||||
|
||||
def get_br_names(self):
|
||||
return props.write_driver.pin.br
|
||||
|
||||
@property
|
||||
def din_name(self):
|
||||
return props.write_driver.pin.din
|
||||
|
||||
@property
|
||||
def en_name(self):
|
||||
return props.write_driver.pin.en
|
||||
|
||||
def get_w_en_cin(self):
|
||||
"""Get the relative capacitance of a single input"""
|
||||
# This is approximated from SCMOS. It has roughly 5 3x transistor gates.
|
||||
return 5*3
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
"""Adds edges based on inputs/outputs. Overrides base class function."""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
Reference in New Issue
Block a user