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Control logic route changes.

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Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
This commit is contained in:
mrg
2021-03-24 14:32:10 -07:00
parent e144f03b23
commit 4a40e96f6d
4 changed files with 110 additions and 23 deletions
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compiler/modules/control_logic.py
+5 -5
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@@ -333,8 +333,9 @@ class control_logic(design.design):
row += 1
self.place_gated_clk_buf_row(row)
row += 1
self.place_wlen_row(row)
row += 1
if (self.port_type == "rw") or (self.port_type == "r"):
self.place_sen_row(row)
row += 1
if (self.port_type == "rw") or (self.port_type == "w"):
self.place_wen_row(row)
height = self.w_en_gate_inst.uy()
@@ -345,9 +346,8 @@ class control_logic(design.design):
if (self.port_type == "rw") or (self.port_type == "w"):
self.place_rbl_delay_row(row)
row += 1
if (self.port_type == "rw") or (self.port_type == "r"):
self.place_sen_row(row)
row += 1
self.place_wlen_row(row)
row += 1
self.place_delay(row)
height = self.delay_inst.uy()
control_center_y = self.delay_inst.by()