Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

LICENSE

@@ -1,4 +1,4 @@
-Copyright 2017 Regents of the University of California and The Board
+Copyright 2018 Regents of the University of California and The Board
 of Regents for the Oklahoma Agricultural and Mechanical College
 (acting for and on behalf of Oklahoma State University)
 

compiler/bank.py

@@ -23,7 +23,7 @@ class bank(design.design):
                     "bitcell_array",   "sense_amp_array",    "precharge_array",
                     "column_mux_array", "write_driver_array", "tri_gate_array"]
         for mod_name in mod_list:
-            config_mod_name = getattr(OPTS.config, mod_name)
+            config_mod_name = getattr(OPTS, mod_name)
             class_file = reload(__import__(config_mod_name))
             mod_class = getattr(class_file , config_mod_name)
             setattr (self, "mod_"+mod_name, mod_class)

compiler/bitcell_array.py

@@ -21,8 +21,8 @@ class bitcell_array(design.design):
         self.column_size = cols
         self.row_size = rows
 
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.cell = self.mod_bitcell()
         self.add_mod(self.cell)
 

compiler/control_logic.py

@@ -59,15 +59,15 @@ class control_logic(design.design):
         self.inv16 = pinv(16)
         self.add_mod(self.inv16)
 
-        c = reload(__import__(OPTS.config.ms_flop_array))
-        ms_flop_array = getattr(c, OPTS.config.ms_flop_array)
+        c = reload(__import__(OPTS.ms_flop_array))
+        ms_flop_array = getattr(c, OPTS.ms_flop_array)
         self.msf_control = ms_flop_array(name="msf_control",
                                          columns=3,
                                          word_size=3)
         self.add_mod(self.msf_control)
 
-        c = reload(__import__(OPTS.config.replica_bitline))
-        replica_bitline = getattr(c, OPTS.config.replica_bitline)
+        c = reload(__import__(OPTS.replica_bitline))
+        replica_bitline = getattr(c, OPTS.replica_bitline)
         self.replica_bitline = replica_bitline(rows=int(math.ceil(self.num_rows / 10.0)))
         self.add_mod(self.replica_bitline)
 

compiler/delay_chain.py

@@ -24,8 +24,8 @@ class delay_chain(design.design):
         self.num_inverters = 1 + sum(fanout_list)
         self.num_top_half = round(self.num_inverters / 2.0)
         
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()
 
         self.add_pins()

compiler/example_config_freepdk45.py

@@ -4,24 +4,6 @@ num_banks = 1
 
 tech_name = "freepdk45"
 
-output_path = "./temp"
+output_path = "temp"
 output_name = "sram_2_16_1_freepdk45"
 
-decoder = "hierarchical_decoder"
-ms_flop = "ms_flop"
-ms_flop_array = "ms_flop_array"
-control_logic = "control_logic"
-bitcell_array = "bitcell_array"
-sense_amp = "sense_amp"
-sense_amp_array = "sense_amp_array"
-precharge_array = "precharge_array"
-column_mux_array = "single_level_column_mux_array"
-write_driver = "write_driver"
-write_driver_array = "write_driver_array"
-tri_gate = "tri_gate"
-tri_gate_array = "tri_gate_array"
-wordline_driver = "wordline_driver"
-replica_bitline = "replica_bitline"
-replica_bitcell = "replica_bitcell"
-bitcell = "bitcell"
-delay_chain = "delay_chain"

compiler/example_config_scn3me_subm.py

@@ -4,24 +4,6 @@ num_banks = 1
 
 tech_name = "scn3me_subm"
 
-output_path = "./temp"
+output_path = "temp"
 output_name = "sram_2_16_1_scn3me_subm"
 
-decoder = "hierarchical_decoder"
-ms_flop = "ms_flop"
-ms_flop_array = "ms_flop_array"
-control_logic = "control_logic"
-bitcell_array = "bitcell_array"
-sense_amp = "sense_amp"
-sense_amp_array = "sense_amp_array"
-precharge_array = "precharge_array"
-column_mux_array = "single_level_column_mux_array"
-write_driver = "write_driver"
-write_driver_array = "write_driver_array"
-tri_gate = "tri_gate"
-tri_gate_array = "tri_gate_array"
-wordline_driver = "wordline_driver"
-replica_bitline = "replica_bitline"
-replica_bitcell = "replica_bitcell"
-bitcell = "bitcell"
-delay_chain = "delay_chain"

compiler/globals.py

@@ -145,18 +145,14 @@ def read_config(config_file):
     # Import the configuration file of which modules to use
     debug.info(1, "Configuration file is " + config_file + ".py")
     try:
-        OPTS.config = importlib.import_module(file_name) 
+        config = importlib.import_module(file_name) 
     except:
         debug.error("Unable to read configuration file: {0}".format(config_file),2)
 
-    # This path must be setup after the config file.
-    try:
-        # If path not set on command line, try config file.
-        if OPTS.output_path=="":
-            OPTS.output_path=OPTS.config.output_path
-    except:
-        # Default to current directory.
-        OPTS.output_path="."
+    # The config file will over-ride all command line args
+    for k,v in config.__dict__.items():
+        OPTS.__dict__[k]=v
+
     if not OPTS.output_path.endswith('/'):
         OPTS.output_path += "/"
     debug.info(1, "Output saved in " + OPTS.output_path)
@@ -247,7 +243,7 @@ def import_tech():
     debug.info(2,"Importing technology: " + OPTS.tech_name)
 
     # Set the tech to the config file we read in instead of the command line value.
-    OPTS.tech_name = OPTS.config.tech_name
+    OPTS.tech_name = OPTS.tech_name
     
     
         # environment variable should point to the technology dir

compiler/hierarchical_decoder.py

@@ -21,8 +21,8 @@ class hierarchical_decoder(design.design):
     def __init__(self, rows):
         design.design.__init__(self, "hierarchical_decoder_{0}rows".format(rows))
 
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell_height = self.mod_bitcell.height
 
         self.pre2x4_inst = []

compiler/hierarchical_predecode.py

@@ -19,8 +19,8 @@ class hierarchical_predecode(design.design):
         self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
         design.design.__init__(self, name="pre{0}x{1}".format(self.number_of_inputs,self.number_of_outputs))
 
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell_height = self.mod_bitcell.height
 
     

compiler/ms_flop_array.py

@@ -20,8 +20,8 @@ class ms_flop_array(design.design):
         design.design.__init__(self, name)
         debug.info(1, "Creating {}".format(self.name))
 
-        c = reload(__import__(OPTS.config.ms_flop))
-        self.mod_ms_flop = getattr(c, OPTS.config.ms_flop)
+        c = reload(__import__(OPTS.ms_flop))
+        self.mod_ms_flop = getattr(c, OPTS.ms_flop)
         self.ms = self.mod_ms_flop("ms_flop")
         self.add_mod(self.ms)
 

compiler/openram.py

@@ -39,19 +39,19 @@ globals.print_banner()
 globals.init_openram(args[0])
 
 # Check if all arguments are integers for bits, size, banks
-if type(OPTS.config.word_size)!=int:
-    debug.error("{0} is not an integer in config file.".format(OPTS.config.word_size))
-if type(OPTS.config.num_words)!=int:
-    debug.error("{0} is not an integer in config file.".format(OPTS.config.sram_size))
-if type(OPTS.config.num_banks)!=int:
-    debug.error("{0} is not an integer in config file.".format(OPTS.config.num_banks))
+if type(OPTS.word_size)!=int:
+    debug.error("{0} is not an integer in config file.".format(OPTS.word_size))
+if type(OPTS.num_words)!=int:
+    debug.error("{0} is not an integer in config file.".format(OPTS.sram_size))
+if type(OPTS.num_banks)!=int:
+    debug.error("{0} is not an integer in config file.".format(OPTS.num_banks))
 
-if not OPTS.config.tech_name:
+if not OPTS.tech_name:
     debug.error("Tech name must be specified in config file.")
 
-word_size = OPTS.config.word_size
-num_words = OPTS.config.num_words
-num_banks = OPTS.config.num_banks
+word_size = OPTS.word_size
+num_words = OPTS.num_words
+num_banks = OPTS.num_banks
 
 if (OPTS.output_name == ""):
     OPTS.output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,

compiler/options.py

@@ -4,7 +4,8 @@ import os
 
 class options(optparse.Values):
     """
-    Class for holding all of the OpenRAM options.
+    Class for holding all of the OpenRAM options. All of these options can be over-riden in a configuration file
+    that is the sole required command-line positional argument for openram.py.
     """
 
     # This is the technology directory.
@@ -12,7 +13,8 @@ class options(optparse.Values):
     # This is the name of the technology.
     tech_name = ""
     # This is the temp directory where all intermediate results are stored.
-    openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
+    #openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
+    openram_temp = "/Users/{}/openram_temp/".format(getpass.getuser())
     # This is the verbosity level to control debug information. 0 is none, 1
     # is minimal, etc.
     debug_level = 0
@@ -35,8 +37,29 @@ class options(optparse.Values):
     # Use detailed LEF blockages
     detailed_blockages = True
     # Define the output file paths
-    output_path = ""
+    output_path = "."
     # Define the output file base name
-    output_name = ""
+    output_name = "sram"
     # Use analytical delay models by default rather than (slow) characterization
     analytical_delay = True
+
+    # These are the default modules that can be over-riden
+    decoder = "hierarchical_decoder"
+    ms_flop = "ms_flop"
+    ms_flop_array = "ms_flop_array"
+    control_logic = "control_logic"
+    bitcell_array = "bitcell_array"
+    sense_amp = "sense_amp"
+    sense_amp_array = "sense_amp_array"
+    precharge_array = "precharge_array"
+    column_mux_array = "single_level_column_mux_array"
+    write_driver = "write_driver"
+    write_driver_array = "write_driver_array"
+    tri_gate = "tri_gate"
+    tri_gate_array = "tri_gate_array"
+    wordline_driver = "wordline_driver"
+    replica_bitline = "replica_bitline"
+    replica_bitcell = "replica_bitcell"
+    bitcell = "bitcell"
+    delay_chain = "delay_chain"
+

compiler/pinv.py

@@ -17,8 +17,8 @@ class pinv(pgate.pgate):
     from center of rail to rail..  The route_output will route the
     output to the right side of the cell for easier access.
     """
-    c = reload(__import__(OPTS.config.bitcell))
-    bitcell = getattr(c, OPTS.config.bitcell)
+    c = reload(__import__(OPTS.bitcell))
+    bitcell = getattr(c, OPTS.bitcell)
 
     unique_id = 1
     

compiler/pnand2.py

@@ -12,8 +12,8 @@ class pnand2(pgate.pgate):
     This model use ptx to generate a 2-input nand within a cetrain height.
     """
 
-    c = reload(__import__(OPTS.config.bitcell))
-    bitcell = getattr(c, OPTS.config.bitcell)
+    c = reload(__import__(OPTS.bitcell))
+    bitcell = getattr(c, OPTS.bitcell)
 
     unique_id = 1
     

compiler/pnand3.py

@@ -12,8 +12,8 @@ class pnand3(pgate.pgate):
     This model use ptx to generate a 2-input nand within a cetrain height.
     """
 
-    c = reload(__import__(OPTS.config.bitcell))
-    bitcell = getattr(c, OPTS.config.bitcell)
+    c = reload(__import__(OPTS.bitcell))
+    bitcell = getattr(c, OPTS.bitcell)
 
     unique_id = 1
     

compiler/pnor2.py

@@ -12,8 +12,8 @@ class pnor2(pgate.pgate):
     This model use ptx to generate a 2-input nor within a cetrain height.
     """
 
-    c = reload(__import__(OPTS.config.bitcell))
-    bitcell = getattr(c, OPTS.config.bitcell)
+    c = reload(__import__(OPTS.bitcell))
+    bitcell = getattr(c, OPTS.bitcell)
 
     unique_id = 1
     

compiler/precharge.py

@@ -16,8 +16,8 @@ class precharge(pgate.pgate):
         pgate.pgate.__init__(self, name)
         debug.info(2, "create single precharge cell: {0}".format(name))
 
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()
         
         self.beta = parameter["beta"]

compiler/replica_bitline.py

@@ -18,14 +18,14 @@ class replica_bitline(design.design):
     def __init__(self, rows, name="replica_bitline"):
         design.design.__init__(self, name)
 
-        g = reload(__import__(OPTS.config.delay_chain))
-        self.mod_delay_chain = getattr(g, OPTS.config.delay_chain)
+        g = reload(__import__(OPTS.delay_chain))
+        self.mod_delay_chain = getattr(g, OPTS.delay_chain)
 
-        g = reload(__import__(OPTS.config.replica_bitcell))
-        self.mod_replica_bitcell = getattr(g, OPTS.config.replica_bitcell)
+        g = reload(__import__(OPTS.replica_bitcell))
+        self.mod_replica_bitcell = getattr(g, OPTS.replica_bitcell)
 
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
 
         for pin in ["en", "out", "vdd", "gnd"]:
             self.add_pin(pin)

compiler/sense_amp_array.py

@@ -14,8 +14,8 @@ class sense_amp_array(design.design):
         design.design.__init__(self, "sense_amp_array")
         debug.info(1, "Creating {0}".format(self.name))
 
-        c = reload(__import__(OPTS.config.sense_amp))
-        self.mod_sense_amp = getattr(c, OPTS.config.sense_amp)
+        c = reload(__import__(OPTS.sense_amp))
+        self.mod_sense_amp = getattr(c, OPTS.sense_amp)
         self.amp = self.mod_sense_amp("sense_amp")
         self.add_mod(self.amp)
 

compiler/single_level_column_mux.py

@@ -16,8 +16,8 @@ class single_level_column_mux(design.design):
         design.design.__init__(self, name)
         debug.info(2, "create single columnmux cell: {0}".format(name))
 
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()
         
         self.ptx_width = tx_size * drc["minwidth_tx"]

compiler/sram.py

@@ -19,18 +19,18 @@ class sram(design.design):
 
     def __init__(self, word_size, num_words, num_banks, name):
 
-        c = reload(__import__(OPTS.config.control_logic))
-        self.mod_control_logic = getattr(c, OPTS.config.control_logic)
+        c = reload(__import__(OPTS.control_logic))
+        self.mod_control_logic = getattr(c, OPTS.control_logic)
         
-        c = reload(__import__(OPTS.config.ms_flop_array))
-        self.mod_ms_flop_array = getattr(c, OPTS.config.ms_flop_array)
+        c = reload(__import__(OPTS.ms_flop_array))
+        self.mod_ms_flop_array = getattr(c, OPTS.ms_flop_array)
         
-        c = reload(__import__(OPTS.config.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.config.bitcell)
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
         self.bitcell = self.mod_bitcell()
 
-        c = reload(__import__(OPTS.config.ms_flop))
-        self.mod_ms_flop = getattr(c, OPTS.config.ms_flop)
+        c = reload(__import__(OPTS.ms_flop))
+        self.mod_ms_flop = getattr(c, OPTS.ms_flop)
         self.ms_flop = self.mod_ms_flop()
         
 

compiler/tests/config_20_freepdk45.py

@@ -8,21 +8,3 @@ tech_name = "freepdk45"
 output_path = "/tmp/freepdk45_sram"
 output_name = "sram_2_16_1_freepdk45"
 
-decoder = "hierarchical_decoder"
-ms_flop = "ms_flop"
-ms_flop_array = "ms_flop_array"
-control_logic = "control_logic"
-bitcell_array = "bitcell_array"
-sense_amp = "sense_amp"
-sense_amp_array = "sense_amp_array"
-precharge_array = "precharge_array"
-column_mux_array = "single_level_column_mux_array"
-write_driver = "write_driver"
-write_driver_array = "write_driver_array"
-tri_gate = "tri_gate"
-tri_gate_array = "tri_gate_array"
-wordline_driver = "wordline_driver"
-replica_bitline = "replica_bitline"
-replica_bitcell = "replica_bitcell"
-bitcell = "bitcell"
-delay_chain = "delay_chain"

compiler/tests/config_20_scn3me_subm.py

@@ -8,21 +8,3 @@ tech_name = "scn3me_subm"
 output_path = "/tmp/scn3me_subm_mysram"
 output_name = "sram_2_16_1_scn3me_subm"
 
-decoder = "hierarchical_decoder"
-ms_flop = "ms_flop"
-ms_flop_array = "ms_flop_array"
-control_logic = "control_logic"
-bitcell_array = "bitcell_array"
-sense_amp = "sense_amp"
-sense_amp_array = "sense_amp_array"
-precharge_array = "precharge_array"
-column_mux_array = "single_level_column_mux_array"
-write_driver = "write_driver"
-write_driver_array = "write_driver_array"
-tri_gate = "tri_gate"
-tri_gate_array = "tri_gate_array"
-wordline_driver = "wordline_driver"
-replica_bitline = "replica_bitline"
-replica_bitcell = "replica_bitcell"
-bitcell = "bitcell"
-delay_chain = "delay_chain"

compiler/tri_gate_array.py

@@ -14,8 +14,8 @@ class tri_gate_array(design.design):
         design.design.__init__(self, "tri_gate_array")
         debug.info(1, "Creating {0}".format(self.name))
 
-        c = reload(__import__(OPTS.config.tri_gate))
-        self.mod_tri_gate = getattr(c, OPTS.config.tri_gate)
+        c = reload(__import__(OPTS.tri_gate))
+        self.mod_tri_gate = getattr(c, OPTS.tri_gate)
         self.tri = self.mod_tri_gate("tri_gate")
         self.add_mod(self.tri)
 

compiler/verify/magic.py

@@ -168,9 +168,9 @@ def run_drc(cell_name, gds_name, extract=False):
         for line in results:
             if "error tiles" in line:
                 debug.info(0,line.rstrip("\n"))
-        debug.error("{0}\tErrors: {1}".format(cell_name, errors))
+        debug.error("DRC Errors {0}\t{1}".format(cell_name, errors))
     else:
-        debug.info(1, "{0}\tErrors: {1}".format(cell_name, errors))
+        debug.info(1, "DRC Errors {0}\t{1}".format(cell_name, errors))
 
     return errors
 

compiler/write_driver_array.py

@@ -15,8 +15,8 @@ class write_driver_array(design.design):
         design.design.__init__(self, "write_driver_array")
         debug.info(1, "Creating {0}".format(self.name))
 
-        c = reload(__import__(OPTS.config.write_driver))
-        self.mod_write_driver = getattr(c, OPTS.config.write_driver)
+        c = reload(__import__(OPTS.write_driver))
+        self.mod_write_driver = getattr(c, OPTS.write_driver)
         self.driver = self.mod_write_driver("write_driver")
         self.add_mod(self.driver)
 

technology/setup_scripts/setup_openram_freepdk45.py

@@ -22,10 +22,16 @@ os.environ["MGC_TMPDIR"] = "/tmp"
 ###########################
 #OpenRAM Paths
 
-DRCLVS_HOME= PDK_DIR+"/ncsu_basekit/techfile/calibre"
+try:
+    DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME"))
+except:
+    DRCLVS_HOME= PDK_DIR+"/ncsu_basekit/techfile/calibre"
 os.environ["DRCLVS_HOME"] = DRCLVS_HOME
 
-os.environ["SPICE_MODEL_DIR"] = PDK_DIR+"/ncsu_basekit/models/hspice/tran_models/models_nom"
+try:
+    SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
+except:
+    os.environ["SPICE_MODEL_DIR"] = PDK_DIR+"/ncsu_basekit/models/hspice/tran_models/models_nom"
 
 ##########################
 #Paths required for OPENRAM to function

technology/setup_scripts/setup_openram_scn3me_subm.py

@@ -19,10 +19,14 @@ os.environ["MGC_TMPDIR"] = "/tmp"
 
 ###########################
 # OpenRAM Paths
-OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
-DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech"
+
+try:
+    DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME"))
+except:
+    OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
+    DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech"
 os.environ["DRCLVS_HOME"] = DRCLVS_HOME
-# You can override the spice model diretory in the environment
+
 try:
     SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
 except: