luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-22 06:07:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

Change bitcell array name to match

Browse Source
This commit is contained in:
mrg
2020-06-10 14:54:20 -07:00
parent f2c45a230e
commit 469cd260b9
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/05_bitcell_1rw_1r_array_test.py → compiler/tests/05_bitcell_array_1rw_1r_test.py
+1 -1
View File
@@ -17,7 +17,7 @@ import debug
#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
class bitcell_1rw_1r_array_test(openram_test):
class bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))