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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Fixed control problems (probably)
Extended functional tests for 15 cycles (slow, but more checking) Fixed s_en to be gated AFTER the RBL.
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@@ -95,16 +95,10 @@ class control_logic(design.design):
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height=dff_height)
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self.add_mod(self.and2)
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if self.port_type=="rw":
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self.rbl_driver = factory.create(module_type="pand2",
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size=self.num_cols,
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height=dff_height)
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self.add_mod(self.rbl_driver)
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elif self.port_type=="r":
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self.rbl_driver = factory.create(module_type="pbuf",
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size=self.num_cols,
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height=dff_height)
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self.add_mod(self.rbl_driver)
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self.rbl_driver = factory.create(module_type="pbuf",
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size=self.num_cols,
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height=dff_height)
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self.add_mod(self.rbl_driver)
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# clk_buf drives a flop for every address and control bit
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@@ -607,12 +601,8 @@ class control_logic(design.design):
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self.rbl_inst=self.add_inst(name="rbl_driver",
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mod=self.rbl_driver)
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if self.port_type == "rw":
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# input: gated_clk_bar, we_bar, output: rbl_wl
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self.connect_inst(["gated_clk_bar", "we_bar", "rbl_wl", "vdd", "gnd"])
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elif self.port_type == "r":
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# input: gated_clk_bar, output: rbl_wl
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self.connect_inst(["gated_clk_bar", "rbl_wl", "vdd", "gnd"])
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# input: gated_clk_bar, output: rbl_wl
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self.connect_inst(["gated_clk_bar", "rbl_wl", "vdd", "gnd"])
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def place_rbl_row(self,row):
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x_off = self.control_x_offset
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@@ -665,7 +655,7 @@ class control_logic(design.design):
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# GATE FOR S_EN
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self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
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mod=self.sen_and2)
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self.connect_inst(["pre_s_en", "gated_clk_bar", "s_en", "vdd", "gnd"])
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self.connect_inst(["pre_s_en", "we_bar", "s_en", "vdd", "gnd"])
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def place_sen_row(self,row):
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@@ -684,7 +674,7 @@ class control_logic(design.design):
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def route_sen(self):
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sen_map = zip(["B"], ["gated_clk_bar"])
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sen_map = zip(["B"], ["we_bar"])
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self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)
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out_pos = self.delay_inst.get_pin("out").bc()
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