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https://github.com/VLSIDA/OpenRAM.git
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Fixed control problems (probably)
Extended functional tests for 15 cycles (slow, but more checking) Fixed s_en to be gated AFTER the RBL.
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@@ -51,11 +51,12 @@ class functional(simulation):
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self.initialize_wmask()
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# Number of checks can be changed
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self.num_cycles = 2
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self.num_cycles = 15
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self.stored_words = {}
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self.write_check = []
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self.read_check = []
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def initialize_wmask(self):
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self.wmask = ""
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if self.write_size is not None:
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@@ -294,9 +295,7 @@ class functional(simulation):
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self.stim = stimuli(self.sf,self.corner)
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#Write include statements
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self.sram_sp_file = "{}sram.sp".format(OPTS.openram_temp)
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shutil.copy(self.sp_file, self.sram_sp_file)
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self.stim.write_include(self.sram_sp_file)
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self.stim.write_include(self.sp_file)
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#Write Vdd/Gnd statements
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self.sf.write("\n* Global Power Supplies\n")
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