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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-06 17:35:28 +02:00
Connected wmask in the spice netlist.
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@@ -290,6 +290,18 @@ class functional(simulation):
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for port in self.readwrite_ports:
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self.stim.gen_pwl("WEB{}".format(port), self.cycle_times , self.web_values[port], self.period, self.slew, 0.05)
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# Generate wmask bits
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for port in self.write_ports:
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self.sf.write("\n* Generation of wmask signals\n")
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if (self.write_size != self.word_size):
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num_wmask = int(self.word_size / self.write_size)
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for bit in range(num_wmask):
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sig_name = "WMASK{0}_{1} ".format(port, bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period,
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self.slew, 0.05)
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# self.stim.gen_pwl(sig_name, self.cycle_times, self.wmask_values[port][bit], self.period,
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# self.slew, 0.05)
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# Generate CLK signals
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for port in self.all_ports:
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self.stim.gen_pulse(sig_name="{0}{1}".format(tech.spice["clk"], port),
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@@ -79,6 +79,7 @@ class simulation():
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# Three dimensional list to handle each addr and data bits for wach port over the number of checks
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self.addr_values = [[[] for bit in range(self.addr_size)] for port in self.all_ports]
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self.data_values = [[[] for bit in range(self.word_size)] for port in self.write_ports]
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self.wmask_values = [[[] for bit in range(self.num_wmask)] for port in self.write_ports]
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# For generating comments in SPICE stimulus
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self.cycle_comments = []
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@@ -130,6 +131,20 @@ class simulation():
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else:
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debug.error("Non-binary address string",1)
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bit -= 1
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def add_wmask(self, wmask, port):
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""" Add the array of address values """
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debug.check(len(wmask) == self.num_wmask, "Invalid wmask size.")
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bit = self.addr_size - 1
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for c in wmask:
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if c == "0":
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self.wmask_values[port][bit].append(0)
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elif c == "1":
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self.wmask_values[port][bit].append(1)
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else:
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debug.error("Non-binary address string", 1)
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bit -= 1
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def add_write(self, comment, address, data, port):
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""" Add the control values for a write cycle. """
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@@ -281,13 +296,14 @@ class simulation():
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for port in range(total_ports):
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if (port in read_index) and (port in write_index):
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pin_names.append("WEB{0}".format(port))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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if (self.write_size != self.word_size):
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num_wmask = int(self.word_size/self.write_size)
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for bit in range(num_wmask):
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pin_names.append("WMASK{0}_{1}".format(port,bit))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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for read_output in read_index:
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for i in range(dbits):
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