mirror of https://github.com/VLSIDA/OpenRAM.git
Fix via directions in s8 col mux
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parent
a1c7474f80
commit
45b0601e4b
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@ -7,7 +7,7 @@
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#
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#
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import design
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import design
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import debug
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import debug
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from tech import layer
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from tech import layer, preferred_directions
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from vector import vector
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from vector import vector
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from sram_factory import factory
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from sram_factory import factory
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from globals import OPTS
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from globals import OPTS
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@ -33,10 +33,15 @@ class single_level_column_mux_array(design.design):
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if "li" in layer:
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if "li" in layer:
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self.col_mux_stack = self.li_stack
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self.col_mux_stack = self.li_stack
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self.col_mux_stack_pitch = self.li_pitch
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self.col_mux_stack_pitch = self.m1_pitch
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else:
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else:
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self.col_mux_stack = self.m1_stack
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self.col_mux_stack = self.m1_stack
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self.col_mux_stack_pitch = self.m1_pitch
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self.col_mux_stack_pitch = self.m1_pitch
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if preferred_directions[self.col_mux_stack[0]] == "V":
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self.via_directions = ("H", "H")
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else:
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self.via_directions = "pref"
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self.create_netlist()
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self.create_netlist()
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if not OPTS.netlist_only:
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if not OPTS.netlist_only:
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@ -173,7 +178,8 @@ class single_level_column_mux_array(design.design):
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self.get_pin("sel_{}".format(sel_index)).cy())
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self.get_pin("sel_{}".format(sel_index)).cy())
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# Add the poly contact with a shift to account for the rotation
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# Add the poly contact with a shift to account for the rotation
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self.add_via_center(layers=self.poly_stack,
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self.add_via_center(layers=self.poly_stack,
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offset=offset)
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offset=offset,
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directions=self.via_directions)
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self.add_path("poly", [offset, gate_offset])
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self.add_path("poly", [offset, gate_offset])
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def route_bitlines(self):
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def route_bitlines(self):
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@ -224,11 +230,13 @@ class single_level_column_mux_array(design.design):
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# This via is on the right of the wire
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# This via is on the right of the wire
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self.add_via_center(layers=self.col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=bl_out_offset)
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offset=bl_out_offset,
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directions=self.via_directions)
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# This via is on the left of the wire
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# This via is on the left of the wire
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self.add_via_center(layers=self.col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=br_out_offset)
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offset=br_out_offset,
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directions=self.via_directions)
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else:
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else:
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self.add_path(self.col_mux_stack[2], [bl_out_offset, bl_offset])
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self.add_path(self.col_mux_stack[2], [bl_out_offset, bl_offset])
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@ -236,10 +244,12 @@ class single_level_column_mux_array(design.design):
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# This via is on the right of the wire
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# This via is on the right of the wire
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self.add_via_center(layers=self.col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=bl_out_offset)
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offset=bl_out_offset,
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directions=self.via_directions)
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# This via is on the left of the wire
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# This via is on the left of the wire
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self.add_via_center(layers=self.col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=br_out_offset)
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offset=br_out_offset,
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directions=self.via_directions)
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def get_drain_cin(self):
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the NMOS pass TX"""
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"""Get the relative capacitance of the drain of the NMOS pass TX"""
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