mirror of https://github.com/VLSIDA/OpenRAM.git
Reduce beta test. Remove other betas. Beta doesn't work well due to simplified rules.
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@ -25,8 +25,8 @@ class pinv_test(unittest.TestCase):
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import pinv
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import pinv
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import tech
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import tech
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debug.info(2, "Checking 1x beta=4 size inverter")
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debug.info(2, "Checking 1x beta=3 size inverter")
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tx = pinv.pinv(size=1, beta=4)
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tx = pinv.pinv(size=1, beta=3)
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self.local_check(tx)
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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OPTS.check_lvsdrc = True
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