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Added wmask to lib.py.

This commit is contained in:
jsowash 2019-09-04 09:29:45 -07:00
parent 1a72070f04
commit 452cc5e443
2 changed files with 23 additions and 7 deletions
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16
compiler/characterizer/lib.py
View File

@ -109,6 +109,8 @@ class lib:
#set the read and write port as inputs. #set the read and write port as inputs.
self.write_data_bus(port) self.write_data_bus(port)
self.write_addr_bus(port) self.write_addr_bus(port)
if self.sram.write_size:
self.write_wmask_bus(port)
self.write_control_pins(port) #need to split this into sram and port control signals self.write_control_pins(port) #need to split this into sram and port control signals
self.write_clk_timing_power(port) self.write_clk_timing_power(port)
@ -400,6 +402,20 @@ class lib:
self.lib.write(" }\n") self.lib.write(" }\n")
self.lib.write(" }\n\n") self.lib.write(" }\n\n")
def write_wmask_bus(self, port):
""" Adds addr bus timing results."""
self.lib.write(" bus(wmask{0}){{\n".format(port))
self.lib.write(" bus_type : wmask; \n")
self.lib.write(" direction : input; \n")
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"] / 1000))
self.lib.write(" max_transition : {0};\n".format(self.slews[-1]))
self.lib.write(" pin(wmask{0}[{1}:0])".format(port, self.sram.num_wmasks - 1))
self.lib.write("{\n")
self.write_FF_setuphold(port)
self.lib.write(" }\n")
self.lib.write(" }\n\n")
def write_control_pins(self, port): def write_control_pins(self, port):
""" Adds control pins timing results.""" """ Adds control pins timing results."""

14
compiler/modules/write_mask_and_array.py
View File

@ -107,16 +107,11 @@ class write_mask_and_array(design.design):
self.nand2 = factory.create(module_type="pnand2") self.nand2 = factory.create(module_type="pnand2")
supply_pin=self.nand2.get_pin("vdd") supply_pin=self.nand2.get_pin("vdd")
# Create the enable pin that connects all write mask AND array's B pins # Create the enable pin that connects all write mask AND array's B pins
beg_en_pin = self.and2_insts[0].get_pin("B") beg_en_pin = self.and2_insts[0].get_pin("B")
end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B") end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B")
if self.port == 0: if self.port % 2:
self.add_layout_pin(text="en", # Extend metal3 to edge of AND array in multiport
layer="metal3",
offset=beg_en_pin.bc(),
width=end_en_pin.cx() - beg_en_pin.cx())
else:
en_to_edge = self.and2.width - beg_en_pin.cx() en_to_edge = self.and2.width - beg_en_pin.cx()
self.add_layout_pin(text="en", self.add_layout_pin(text="en",
layer="metal3", layer="metal3",
@ -126,6 +121,11 @@ class write_mask_and_array(design.design):
offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
self.add_via_center(layers=("metal2", "via2", "metal3"), self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
else:
self.add_layout_pin(text="en",
layer="metal3",
offset=beg_en_pin.bc(),
width=end_en_pin.cx() - beg_en_pin.cx())
for i in range(self.num_wmasks): for i in range(self.num_wmasks):
# Copy remaining layout pins # Copy remaining layout pins