luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Make sure channel route is below s_en

This commit is contained in:
mrg 2021-06-04 07:14:49 -07:00
parent 537fd6eff9
commit 4107c983e2
1 changed files with 18 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
compiler/sram/sram_1bank.py
View File

@ -385,6 +385,7 @@ class sram_1bank(sram_base):
if len(route_map) > 0: if len(route_map) > 0:
# This layer stack must be different than the data dff layer stack
layer_stack = self.m1_stack layer_stack = self.m1_stack
if port == 0: if port == 0:
@ -394,7 +395,7 @@ class sram_1bank(sram_base):
offset=offset, offset=offset,
layer_stack=layer_stack, layer_stack=layer_stack,
parent=self) parent=self)
# This causes problem in magic since it sometimes cannot extract connectivity of isntances # This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices. # with no active devices.
self.add_inst(cr.name, cr) self.add_inst(cr.name, cr)
self.connect_inst([]) self.connect_inst([])
@ -406,7 +407,7 @@ class sram_1bank(sram_base):
offset=offset, offset=offset,
layer_stack=layer_stack, layer_stack=layer_stack,
parent=self) parent=self)
# This causes problem in magic since it sometimes cannot extract connectivity of isntances # This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices. # with no active devices.
self.add_inst(cr.name, cr) self.add_inst(cr.name, cr)
self.connect_inst([]) self.connect_inst([])
@ -441,21 +442,21 @@ class sram_1bank(sram_base):
if len(route_map) > 0: if len(route_map) > 0:
# The write masks will have blockages on M1 # This layer stack must be different than the column addr dff layer stack
# if self.num_wmasks > 0 and port in self.write_ports:
# layer_stack = self.m3_stack
# else:
# layer_stack = self.m1_stack
layer_stack = self.m3_stack layer_stack = self.m3_stack
if port == 0: if port == 0:
# This is relative to the bank at 0,0 or the s_en which is routed on M3 also
s_en_bot = self.control_logic_insts[port].get_pin("s_en").by()
y_offset = min(0, s_en_bot) - self.data_bus_size[port] + 2 * self.m3_pitch
offset = vector(self.control_logic_insts[port].rx() + self.dff.width, offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
- self.data_bus_size[port] + 2 * self.m3_pitch) y_offset)
cr = channel_route(netlist=route_map, cr = channel_route(netlist=route_map,
offset=offset, offset=offset,
layer_stack=layer_stack, layer_stack=layer_stack,
parent=self) parent=self)
if add_routes: if add_routes:
# This causes problem in magic since it sometimes cannot extract connectivity of isntances # This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices. # with no active devices.
self.add_inst(cr.name, cr) self.add_inst(cr.name, cr)
self.connect_inst([]) self.connect_inst([])
@ -463,14 +464,16 @@ class sram_1bank(sram_base):
else: else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
else: else:
s_en_top = self.control_logic_insts[port].get_pin("s_en").uy()
y_offset = max(self.bank.height, s_en_top) + self.m3_pitch
offset = vector(0, offset = vector(0,
self.bank.height + self.m3_pitch) y_offset)
cr = channel_route(netlist=route_map, cr = channel_route(netlist=route_map,
offset=offset, offset=offset,
layer_stack=layer_stack, layer_stack=layer_stack,
parent=self) parent=self)
if add_routes: if add_routes:
# This causes problem in magic since it sometimes cannot extract connectivity of isntances # This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices. # with no active devices.
self.add_inst(cr.name, cr) self.add_inst(cr.name, cr)
self.connect_inst([]) self.connect_inst([])