mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 11:08:01 +02:00
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
This commit is contained in:
Michael Timothy Grimes
Executable
+42
@@ -0,0 +1,42 @@
|
||||
#!/usr/bin/env python3
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"""
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Run regresion tests on a parameterized bitcell
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"""
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import unittest
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||||
from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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||||
from globals import OPTS
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||||
import debug
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||||
OPTS = globals.OPTS
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@unittest.skip("SKIPPING 04_bitcell_1rw_1r_test")
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class bitcell_1rw_1r_test(openram_test):
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def runTest(self):
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OPTS.bitcell = "bitcell_1rw_1r"
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from bitcell import bitcell
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from bitcell_1rw_1r import bitcell_1rw_1r
|
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import tech
|
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=0
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OPTS.num_r_ports=1
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debug.info(2, "Bitcell with 1 read/write and 1 read port")
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#tx = bitcell_1rw_1r()
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tx = bitcell()
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self.local_check(tx)
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|
||||
globals.end_openram()
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||||
|
||||
|
||||
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||||
# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
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||||
del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@@ -11,7 +11,7 @@ import globals
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||||
from globals import OPTS
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import debug
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||||
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||||
@unittest.skip("SKIPPING 22_sram_pex_test")
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||||
@unittest.skip("SKIPPING 26_pex_test")
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||||
class sram_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
||||
Executable
+80
@@ -0,0 +1,80 @@
|
||||
#!/usr/bin/env python3
|
||||
"""
|
||||
Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
|
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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|
||||
@unittest.skip("SKIPPING 27_worst_case_delay_test")
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||||
class worst_case_timing_sram_test(openram_test):
|
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|
||||
def runTest(self):
|
||||
OPTS.tech_name = "freepdk45"
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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||||
OPTS.spice_name="hspice"
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||||
OPTS.analytical_delay = False
|
||||
OPTS.trim_netlist = False
|
||||
OPTS.check_lvsdrc = True
|
||||
|
||||
|
||||
# This is a hack to reload the characterizer __init__ with the spice version
|
||||
from importlib import reload
|
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import characterizer
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reload(characterizer)
|
||||
from characterizer import worst_case
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||||
if not OPTS.spice_exe:
|
||||
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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|
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word_size, num_words, num_banks = 2, 16, 1
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=word_size,
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num_words=num_words,
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num_banks=num_banks)
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c.words_per_row=1
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#c.compute_sizes()
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debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
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word_size, num_words, num_banks))
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s = sram(c, name="sram1")
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||||
|
||||
sp_netlist_file = OPTS.openram_temp + "temp.sp"
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||||
s.sp_write(sp_netlist_file)
|
||||
|
||||
if OPTS.use_pex:
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||||
gdsname = OPTS.output_path + s.name + ".gds"
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||||
s.gds_write(gdsname)
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|
||||
import verify
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reload(verify)
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# Output the extracted design if requested
|
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sp_pex_file = OPTS.output_path + s.name + "_pex.sp"
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verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file)
|
||||
sp_sim_file = sp_pex_file
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||||
debug.info(1, "Performing spice simulations with backannotated spice file.")
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||||
else:
|
||||
sp_sim_file = sp_netlist_file
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||||
debug.info(1, "Performing spice simulations with spice netlist.")
|
||||
|
||||
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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||||
wc = worst_case(s.s, sp_sim_file, corner)
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||||
import tech
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||||
loads = [tech.spice["msflop_in_cap"]*4]
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||||
slews = [tech.spice["rise_time"]*2]
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||||
probe_address = "1" * s.s.addr_size
|
||||
probe_data = s.s.word_size - 1
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||||
wc.analyze(probe_address, probe_data, slews, loads)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main()
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||||
@@ -78,214 +78,216 @@ cell (sram_2_16_1_freepdk45){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 948.52275;
|
||||
area : 977.4951374999999;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.0021292;
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||||
when : "CSb0";
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value : 0.0011164579999999999;
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||||
}
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||||
cell_leakage_power : 0;
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||||
bus(DIN){
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
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||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
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||||
bus(DOUT){
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||||
bus(DOUT0){
|
||||
bus_type : DATA;
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||||
direction : output;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
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||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.229, 0.23, 0.234",\
|
||||
"0.23, 0.23, 0.234",\
|
||||
"0.236, 0.236, 0.24");
|
||||
values("0.235, 0.235, 0.239",\
|
||||
"0.235, 0.236, 0.24",\
|
||||
"0.241, 0.242, 0.246");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("2.555, 2.556, 2.568",\
|
||||
"2.555, 2.557, 2.569",\
|
||||
"2.562, 2.563, 2.575");
|
||||
values("2.583, 2.585, 2.612",\
|
||||
"2.584, 2.585, 2.613",\
|
||||
"2.59, 2.592, 2.62");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028");
|
||||
values("0.022, 0.022, 0.03",\
|
||||
"0.022, 0.023, 0.03",\
|
||||
"0.022, 0.022, 0.03");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.111, 0.112, 0.115",\
|
||||
"0.111, 0.111, 0.115",\
|
||||
"0.111, 0.111, 0.116");
|
||||
values("0.078, 0.079, 0.083",\
|
||||
"0.078, 0.079, 0.083",\
|
||||
"0.079, 0.079, 0.083");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
pin(ADDR[3:0]){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.027431397222222223");
|
||||
values("0.03599689694444445");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.027431397222222223");
|
||||
values("0.03599689694444445");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.026240397222222222");
|
||||
values("0.029906643888888886");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.026240397222222222");
|
||||
values("0.029906643888888886");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb";
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
@@ -295,7 +297,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("2.422");
|
||||
}
|
||||
@@ -305,7 +307,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("4.844");
|
||||
}
|
||||
@@ -314,5 +316,6 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,96 +78,98 @@ cell (sram_2_16_1_freepdk45){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 948.52275;
|
||||
area : 977.4951374999999;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.000168;
|
||||
when : "CSb0";
|
||||
value : 0.000179;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN){
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT){
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113");
|
||||
values("0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113");
|
||||
values("0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
pin(ADDR[3:0]){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
@@ -181,7 +183,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
@@ -196,12 +198,12 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
@@ -215,7 +217,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
@@ -229,12 +231,12 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
@@ -248,7 +250,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
@@ -262,30 +264,30 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb";
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
@@ -295,7 +297,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
@@ -305,7 +307,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
@@ -314,5 +316,6 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,214 +78,216 @@ cell (sram_2_16_1_freepdk45){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 948.52275;
|
||||
area : 977.4951374999999;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.0021292;
|
||||
when : "CSb0";
|
||||
value : 0.0011164579999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN){
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT){
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.227, 0.227, 0.231",\
|
||||
"0.227, 0.228, 0.232",\
|
||||
"0.233, 0.234, 0.238");
|
||||
values("0.233, 0.233, 0.237",\
|
||||
"0.233, 0.234, 0.237",\
|
||||
"0.239, 0.24, 0.244");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("2.555, 2.557, 2.569",\
|
||||
"2.556, 2.557, 2.569",\
|
||||
"2.562, 2.563, 2.576");
|
||||
values("2.584, 2.585, 2.611",\
|
||||
"2.584, 2.585, 2.612",\
|
||||
"2.591, 2.592, 2.618");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028");
|
||||
values("0.022, 0.022, 0.03",\
|
||||
"0.022, 0.023, 0.03",\
|
||||
"0.022, 0.023, 0.03");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.11, 0.11, 0.114",\
|
||||
"0.109, 0.11, 0.113",\
|
||||
"0.11, 0.11, 0.114");
|
||||
values("0.076, 0.077, 0.082",\
|
||||
"0.077, 0.077, 0.082",\
|
||||
"0.077, 0.077, 0.082");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
pin(ADDR[3:0]){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.025181683333333333");
|
||||
values("0.03334771594444444");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.025181683333333333");
|
||||
values("0.03334771594444444");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.024945991666666667");
|
||||
values("0.028457026222222223");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.024945991666666667");
|
||||
values("0.028457026222222223");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb";
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
@@ -295,7 +297,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("2.422");
|
||||
}
|
||||
@@ -305,7 +307,7 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("4.844");
|
||||
}
|
||||
@@ -314,5 +316,6 @@ cell (sram_2_16_1_freepdk45){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -314,5 +314,6 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,11 +78,11 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 60176.520000000004;
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000175;
|
||||
value : 0.0009813788999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
@@ -91,7 +91,37 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
@@ -103,57 +133,29 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
values("1.556, 1.576, 1.751",\
|
||||
"1.559, 1.579, 1.754",\
|
||||
"1.624, 1.643, 1.819");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
values("3.445, 3.504, 3.926",\
|
||||
"3.448, 3.507, 3.93",\
|
||||
"3.49, 3.549, 3.972");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
values("0.13, 0.169, 0.574",\
|
||||
"0.13, 0.169, 0.574",\
|
||||
"0.13, 0.169, 0.574");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
values("0.467, 0.49, 0.959",\
|
||||
"0.467, 0.49, 0.959",\
|
||||
"0.47, 0.493, 0.96");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -167,30 +169,30 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -201,30 +203,30 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -234,54 +236,54 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk & !WEb0";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("9.972790277777777");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("9.972790277777777");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk & WEb0";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("8.899322499999998");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("8.899322499999998");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -295,24 +297,25 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("2.344");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("2.344");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
values("4.688");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0");
|
||||
values("4.688");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,11 +78,11 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 60176.520000000004;
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000175;
|
||||
value : 0.000179;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
@@ -91,21 +91,12 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
@@ -119,7 +110,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
@@ -131,9 +122,20 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
@@ -167,7 +169,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
@@ -181,7 +183,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
@@ -201,7 +203,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
@@ -215,7 +217,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
@@ -234,7 +236,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
@@ -248,7 +250,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
@@ -262,26 +264,26 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk & !WEb0";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk & WEb0";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -295,7 +297,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
@@ -305,7 +307,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
@@ -314,5 +316,6 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,11 +78,11 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 60176.520000000004;
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.025716199999999998;
|
||||
value : 0.0009813788999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
@@ -91,7 +91,37 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
@@ -103,57 +133,29 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("1.277, 1.297, 1.475",\
|
||||
"1.28, 1.3, 1.479",\
|
||||
"1.347, 1.367, 1.545");
|
||||
values("1.542, 1.562, 1.738",\
|
||||
"1.545, 1.565, 1.741",\
|
||||
"1.609, 1.629, 1.805");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("3.217, 3.281, 3.71",\
|
||||
"3.22, 3.285, 3.714",\
|
||||
"3.261, 3.325, 3.75");
|
||||
values("3.446, 3.505, 3.924",\
|
||||
"3.45, 3.508, 3.927",\
|
||||
"3.491, 3.55, 3.97");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.122, 0.164, 0.579",\
|
||||
"0.122, 0.164, 0.578",\
|
||||
"0.122, 0.164, 0.58");
|
||||
values("0.129, 0.169, 0.573",\
|
||||
"0.129, 0.169, 0.573",\
|
||||
"0.129, 0.169, 0.573");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.363, 0.396, 0.958",\
|
||||
"0.363, 0.396, 0.957",\
|
||||
"0.366, 0.399, 0.951");
|
||||
values("0.457, 0.481, 0.956",\
|
||||
"0.457, 0.481, 0.956",\
|
||||
"0.459, 0.483, 0.957");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -167,30 +169,30 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -201,30 +203,30 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -234,54 +236,54 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk & !WEb0";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("9.141838916666668");
|
||||
values("9.602821763527778");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("9.141838916666668");
|
||||
values("9.602821763527778");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk & WEb0";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("8.304491694444444");
|
||||
values("8.647938152416664");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("8.304491694444444");
|
||||
values("8.647938152416664");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -295,7 +297,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("2.344");
|
||||
}
|
||||
@@ -305,7 +307,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("4.688");
|
||||
}
|
||||
@@ -314,5 +316,6 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user